Defining signoff and its problems; the impact of multiple power islands and millions of transistors; static timing analysis; the pros and cons of margin; how EDA companies choose their R&D targets.

First of three parts: Less leakage, but uncertainty about reliability, and big challenges with power density and moving designs from one foundry to the next; pin accessibility becomes more difficult; fixed widths; thermal unknowns.

Second of three parts: Development costs; double patterning; ROI; finFETs vs. stacked die; who’s calling the shots; process variability and gate variants; new design rules.

Last of three parts: Parasitics; power density; dynamic power variability; throttling back performance; improving software efficiency and other architectural approaches.

First of three parts: Incompatible tools and methodologies; multivendor tool issues; low-power verification reality check; user issues; the impact of complexity and feature shrinking.

Second of three parts: What’s missing; extra work required; making IP work better; the limits of abstractions; how power will be integrated in the future.

Last of three parts: Determining power intent; keeping up with complexity, but sweating along the way; tool versioning problems; software; merging function and power.

First of three parts: Memory access time; SoC complications; tradeoffs with energy efficiency; external causes of latency; the good and bad of software design; network impacts; dependencies and intrinsic issues.

Last of three parts: Cloud vs. local partitioning; pre-computing; quicker maps; low-power mode and other tradeoffs; the impact of smaller wires; architectural issues; Wide I/O benefits; virtualization.

Second of three parts: Hardware vs. software; energy efficiency issues for memory; the impact of use models; worst-case scenarios and what can go wrong; SMP approaches and issues.

Signoff has become a balancing act between what’s good enough and time-to-market demands.

A look at the array of challenges ahead for semiconductor manufacturing and design.

A look at the challenges of effectively dealing with latency in semiconductor design.

What’s new with power formats and what else can be done to save power in complex SoCs.

Obstacles to achieving more efficient SoC designs and what can be done to overcome them.

A candid discussion about the future of Moore’s Law, multicore, many-core and multiple cores, and the challenge of getting software to be more efficient.

Synopsys CEO Aart de Geus talks about complexity, software and hardware, and the future of design.

What’s changed at the Design Automation Conference and what’s driving those changes in the semiconductor supply chain.

Apache Design’s Aveek Sarkar talks about electromigration, ESD, and the power and thermal challenges ahead in stacked die and at 20nm and beyond.

A look at what’s missing from the ESL tool chain and why it’s important.