Power Bits: Solar Chips And Lower Voltage
Intel working with solar power and 3D stacking
Intel Labs rolled out a novel concept this week—a new CPU architecture that it claims will offer five times the energy efficiency of other Pentium-class processors while offering the ability to run off a postage-stamp sized solar cell.
What’s unique about this approach is that the CPU drops below 10 milliwatts when its workload is load, but can utilize Intel’s burst approach to add in more cores when necessary. Bursting is akin to on-chip virtualization, in that it allows a single application to utilize any available processing resources.
Even more intriguing, though, is Intel’s collaboration with Micron on the latter’s Hybrid Memory Cube, which it claims will add a seven-fold improvement in energy efficiency over DDR3. In case you wondered whether Intel was experimenting with 2.5D and 3D stacked die architectures, this should provide the answer. The HMC is a 3D stacked die package, which greatly improves density and speed by adding multiple layers of chips connected with through-silicon vias. That both shortens the distance and widens the data pipes, while simultaneously requiring less energy to drive signals.
Most researchers look at stacked die as the best way to cut power while also improving performance. The fact that Intel already is collaborating with Micron on this approach opens up some interesting possibilities for the processor giant’s move into the low-power SoC world.
Lower power capacitors and transistors
Researchers at UC Berkeley are using a ferroelectric layer—in this case lead-zirconate-titanate—on an insulator to cut the minimum voltage needed to store a charge in a capacitor. By using this combination the charge can actually be amplified, creating negative capacitance and solving one of the big issues with capacitors.
The initial work was done at 200 degrees Celsius, but new materials are expected to allow this principle to operate at room temperature. They’re also working on putting these materials into transistors, which is where things get even more interesting. One of the big challenges in dropping the voltage inside of SoCs is the minimum needed to safeguard function and prevent data loss through gates. It remains to be seen whether amplifying a charge can actually alter the minimum voltage, but it’s certainly worth a try.
Perhaps even more interesting is who else is funding this effort—Semiconductor Research Corp. and the Office of Naval Research.
–Ed Sperling
Tags: 3D Stacking, Intel, Micron, UC Berkeley