By Ann Steffora Mutschler

With advanced semiconductor technologies infiltrating the automotive market in ever new and exciting ways, there are also challenges to implementation involving power. In fact, power has become a concern in many areas of automotive design.

Consider the Tesla, for example. The dashboard features a 17” touchscreen with the entire vehicle controls. This system is run by two Nvidia Tegra GPUs. Normally this would include a 16-bit CPU, but the CPU doesn’t offer enough performance.

The dashboard of the Tesla with 17" touchscreen display. (Source: Tesla Motors)

This isn’t such a simple tradeoff, though. The Tegras are designed for a tablet. As a result there are electromagnetic interference issues to consider. Moreover, tablets have two- and four-year lifecycles and they operate vastly different environments than an electric car dashboard.

“You have to take that same part and claim that it works from -50 to 150 degrees, that sort of range,” said Aveek Sarkar, vice president of product engineering and support at Apache “With a lot of these designs, taking the same design and applying it for multiple uses will create challenges.”

Sarkar pointed out that many semiconductor companies targeting the automotive market are starting to worry about power analysis and how to reduce the power consumption for chips aimed at automobiles.

Mladen Nizic, engineering director for mixed signal solution at Cadence noted that some automotive devices are power-sensitive by nature. “If you take a tire pressure monitor, for example, it has to collect the energy from motion and it has to be very power-efficient because there is no power supply inside the tire.”

And if there were a system that was monitoring the car continuously, it might actually drain the battery, so there are specific applications that are almost equally low power as a wireless phone, he said. “You have to try to minimize consumption as much as possible.”

Dollars and cents

Alexandre Palus, principal SoC architect at Altera, agreed. He said that in automotive, power translates directly to cash. “BMW and Mercedes have quantified the mileage per gallon that is equivalent to the watt. So depending on how many watts you consume, they will tell you how many miles per gallon you are going to get. At the end of the day, because the European car manufacturer has to pay a tax—the carbon tax—that translates to a certain amount of money from them to pay because of your device. So now when you are selling a device to a carmaker and you say, ‘I’m 2 or 3 or 4 watts,’ or whatever, and to them it’s the amount of money they are going to pay back so the [chip] that consumes less. It is actually a savings for them.”

Because European carmakers are doing this, it may only be a matter of time before it’s also standard practice with Japanese carmakers and in the United States, as well.

Related to power is EMI radiation, which is also a huge concern. “Depending on which application, for instance typically Bluetooth and Zigbee, these are already embedded. Broadband RF is likely next as there are higher speed radios, higher energy – the electromagnetic interference (EMI) is going to become a worse problem,” Sarkar said.

Thermal analysis—how heat effects the chip—is another area gaining traction among semiconductor vendors with devices aimed at the automotive space.

While these are just a few examples of the power challenges in the automotive space, it also represents new opportunities for EDA tools tailored to the specific requirements of this evolving and sophisticated market.

By Ed Sperling
Complexity, tight power budgets, disaggregation of the supply chain and market fragmentation are conspiring to force much tighter partnerships among companies that develop different pieces of an SoC, as well as those that collaborate on even larger systems. This confluence of factors has forced the rules for how companies work together to be rewritten, but even within that framework the reconfigured supply chain is far from perfect.

While companies are choosing partners more carefully, the sheer number of interactions on a complex SoC and the multitude of markets that need to be served means that not everything goes together as well as predicted. IP, for example, is still a black box technology. Software is never completely bug free. And no matter how many use cases are run, errors increase proportionately with complexity.

One question being asked these days is whether is it any worse in a disaggregated ecosystem than at an integrated device manufacturer? The answer is that it depends—on the companies working together, what they’re working on, and how paranoid companies are about sharing their secrets with their partners.

What may be surprising, though, is that the same factors apply even within the same company. Territorial engineering managers or bad relationships between software and hardware teams, or between one office and another in different locations, can turn a problem even within an IDM into an intractable one.

“I’ve seen IDMs that collaborate more poorly under one roof than different companies working together,” said Gregg Bartlett, CTO of GlobalFoundries. “It comes down to the nature of the relationship. I’m talking to some companies five years ahead of tapeout. As effective as the traditional IDM model can be, you also can have a lack of trust within a company.”

Tighter partnerships
One thing that has changed significantly is the number and depth of relationships between companies. That means fewer companies working together, but those that are working together have to be willing to provide far more information to each other than in the past. This is no longer just a simple transaction. It’s an ongoing relationship of dependencies, where you’re only as good as your own partners.

“The early adopters started this five years ago,” said Chris Rowen, CTO at Tensilica. “Leaders emerge and there is a natural connection. But the whole value chain is evolving. Chips are more complex and chipmakers are drawn into hardware, software and the services around the platform. This is why you’re seeing outsourcing of more complete subsystems, which pull together the critical elements of the PHY and drive throughput and power.”

To some extent, it also is a natural way of cleaning up the supply chain. Those with the best technology or the best market reach are natural choices for partnerships, which is why there has been a flurry of acquisitions lately.

“We see a couple reasons why this is happening,” said Amit Rohatgi, vice president of mobile solutions at MIPS. “One is that technology is not only getting complicated, it’s also getting expensive. The 28nm node is not cheap and it’s very complex. A mask set is $2 million. We were getting a lot of lower-cost technology out of China, but even they’re starting to rethink their 28nm strategy. The second reason is that we’re dealing with a new currency. It was frequency, the number of cores and graphics. Now it’s time to market. So if you put two or three pieces together, will it work?”

More often that not, putting those pieces together requires additional engineering. But the rule of thumb is that the more pieces that are integrated by one vendor, the better the results—one of the drivers toward stacked die and subsystems that may consist of an entire die.

“The old outsourced distributed model doesn’t work that well anymore,” observed Mike Gianfagna, vice president of corporate marketing at Atrenta. “The virtual IDM model, where things are put together like they are in a more monolithic organization and very tightly integrated might be one of the only ways to get this to work. The platform idea already has been applied to power distribution and power control. If the strategy works and it can be proven in silicon, then customers will flock to you. But it all has to work together. Predictability is important.”

Even in areas where parts are sold discretely, the tide is shifting toward pre-integration—or at least fully characterizing those parts to play well with others and speed up time to market. Nothing is sold “as is” anymore—not even parts that can be programmed.

“There are still discrete solutions where the selling process is the same,” said John Daane, chairman and CEO of FPGA maker Altera. “But even with DSPs you now get information about how to implement the DSP. The value proposition is still your product, but you’re selling it at the system level. There are two problems that we’re facing. One is the rising cost of design. The second is the rising cost of transistors. When you take into account all factors, the cost of transistors is going up.”

Holes in the supply chain
Aart de Geus, chairman and co-CEO of Synopsys, said that when partnerships work they work well, because both companies have a stake in seeing that partnership succeed. But that doesn’t happen all the time, and it certainly doesn’t happen for a complete system.

“It’s very uneven,” said de Geus. “The degree of collaboration is very high, and we’re seeing it from the EDA community all the way to manufacturing, from IP to tools, and in design and software. There is no question that people who cooperate well with each other get better results, and if you look at virtual IDMs these companies have to work together. Today’s subsystems are yesterday’s board, and any time you can economically reduce risk and complexity you win.”

He’s not alone in that assessment. Grant Pierce, president and CEO of Sonics, terms partnering for creating more complete solutions at the subsystem level “inevitable.”

“Still, there’s no simple way to do that,” he said. “It takes a lot of work on the part of companies building a subsystem. That part is difficult. We touch on enough things that touch on gaps, and the challenge is that all the pieces aren’t in place yet.”

What typically drives those kinds of relationships is a complex solution that is best provided by expertise from more than one company, within a reasonable amount of time, and for a reasonable cost. This works better in some segments than others—particularly commoditized sectors—and it works better in some areas than others, notably those where there is competition or a tight market window—or both.

“It depends on the application,” said Ted Tewksbury, president and CEO of Integrated Device Technology. “It can work on susbsystems if you work together. We developed a flash controller with Micron where they provided the digital controller and we added our expertise in PCI express. The semiconductor industry has reached a level of sophistication where companies recognize their value add, which is why we have an increasing amount of segmentation of the value chain.”

By Ed Sperling
Figuring out a single power budget and mapping out what has become known as holistic power intent for an SoC sounds great on paper, but reality has turned out to be somewhat different.

While system architects still call the shots on how a chip is designed, there is a lot more information flowing in all directions further down the design chain these days. Unlike functionality, which can largely be set by a marketing department, power doesn’t always behave in predictable ways. And no matter how much progress is made on tools, gaps remain.

The challenge is bridging a high-level of abstraction, where the biggest dent can be made in an SoC’s overall power budget, with the back end of the flow, where measurements are accurate but it’s more difficult to make changes. Yet it’s precisely at the back end where problems really show up.

“The gate-level power analysis is much more accurate, but it’s too little too late,” said David “Woody” Norwood, principal applications engineer at Apache Design. “We’re finding power bugs that are logically functionally correct but which waste power.”

Norwood compared it to the New York skyline. When all the lights are on you can see where the power is going, and when all the lights are off it looks dark. But close in on the skyline and you’ll find not all the lights are off or on.

“Big companies are trying to stay within a 15% to 20% error margin for RTL, and some customers are even looking to move that up to 10%,” he said. But design for power isn’t always so predictable.

Opening up communications
One way to deal with power issues is to open up communication across groups that historically have functioned independently. At the place and route level, for example, the architecture is already set in stone. But talking to other teams—particularly software developers—can go a long way toward resolving power issues and preventing others.

“You can do a lot for power optimization in synthesis and place and route because you know the exact power numbers based on capacitance extraction,” said Arvind Narayanan, product marketing manager in Mentor Graphics’ place and route group. “If you’re doing a chip with four power domains you have to stick with those four domains even though you find you may only need three. But you can still have in impact on synthesis, floor planning, clock trees and software. We provide a lot of feedback to the software teams, which can still make changes that are comprehensive.”

This is a new communication channel for power. While there has been regular dialog between software and hardware design teams over performance and timing, power is a relatively new area for discussion. At least part of that is driven by the need for sticking within the power budget, which affects hardware and software, but part of it also due to the fact that hardware teams are now responsible for more of the software content. Still, power may be the glue to bring these two worlds together.

“The missing piece today is the link between the hardware and software,” said Ghislain Kaiser, CEO of Docea Power. “As an industry we have put more focus on the hardware, but with things like MIPI we’re starting to see the same issues coming up. One issue is how to make software companies participate in standardization. What’s becoming clear is that software companies now understand they need to optimize both hardware and software. But there are still many obstacles to making this work. These are not the same cultures and the way they purchase tools are different.”

Establishing feedback loops
Figuring out a common lexicon may be step one. While many people use power and energy interchangeably, there are different time windows for each. Power requires a narrow window because it can create thermal issues in an IC, while energy is more focused on how efficiently a design works and how long the battery lasts—as well as how it’s actually used.

“You have to be very clear about the design decisions you’re trying to solve and the needs to make those decisions,” said Pete Hardee, marketing director at Cadence. “The key limitation in all of this is real activity. Right now there are no ESL power modeling standards and there is a lot of confusion about what’s the system level. What is clear is that one size doesn’t fit all and models alone are not very useful without real activity data.”

He said that for power optimization there are a variety of techniques available such as clock gating, multi-voltage optimization and area/power performance, while there also are macro-architectural techniques available such as voltage islands, power shutoff, dynamic voltage frequency scaling, power shutoff and substrate biasing. But applying those requires a give and take between accuracy and high-level design.

That seems to be the general consensus among chipmakers, as well. Arif Rahman, IC design manager at Altera, said there needs to be a top-down and a bottom-up approach driven by good communication. This is particularly tricky in an FPGA, because programmability can radically change the way a chip is used.

“The same designs can end up with completely different use cases,” said Rahman. “Mixing custom plus standard designs is much more challenging.”

Converging approaches
The big challenge in a complex IC when it comes to power is to comprehend all of the pieces and the impact of one on the other. This is well beyond the the system architect at a high level, or engineers at the back end of the flow. Each of them understands pieces and can identify problems on their side, but there are many more issues that erupt before tapeout and even after a chip is in production and in a consumer’s hands.

“The tools should lead you to the right answer,” said Mike Gianfagna, vice president of marketing at Atrenta. “You start at a high level, add in as much data as you can, and as you move toward tapeout you want vectors that are convergent. But along the way you need to refine that to the point where you get to your target.”

That constant refinement, including more and more elements of the design, is what ultimately will produce a chip with fewer power surprises. And the only way to get there is with all the tools, the data—and better communication among more people working on a design.

By John Blyler & Ed Sperling
For the past couple of process nodes chipmakers have been developing power-saving features that have been largely ignored by OEMs. That’s beginning to change.

The need to do more and faster processing within the same or smaller power budget is forcing significant architectural changes, more efficient software, and new materials into the equation. They are showing up in some of the latest announcements and presentations from companies across the semiconductor industry.

Architectural leaps
David “Dadi” Perlmutter, in his keynote address at the Intel Developer Forum this week, hinted at some architectural changes that will help pave the way for new voice and gesture-recognition interfaces. One involves near-threshold voltage scaling, something he referred to as “versatile performance.” As he put it, “if the platform is not warm enough, you scale down.”

To get to the next steps, Intel will need to add a number of architectural changes. The first will be rolled out next year with a 22nm processor, code-named Haswell, that includes its TriGate or finFET technology. That will be followed by a 14nm chip, which Intel reportedly is already testing.

Intel has been working with a variety of materials, including fully depleted SOI, and it has been experimenting with various gate structures and stacking approaches. But which ones ultimately get used depend on when it becomes economically required to change its processes and manufacturing. The company may buy some time just by using bulk CMOS combined with EUV lithography and 450mm wafer technology, in which it has invested heavily over the past few months. Bigger wafers and commercially viable EUV could well pave the way for advances at the next couple of process nodes.

In a speech prior to IDF, Intel Labs’ Gregory Ruhl talked about the energy benefits of Near Threshold Voltage (NTV) computing using Intel’s IA-32, 32nm CMOS processor technology. The so-called “Claremont” prototype chip relies on an ultra-low voltage circuit to greatly reduce energy consumption. This class of processor operates close to the transistor’s turn-on or threshold voltage—hence the NTV name. Threshold voltages vary with transistor type, but are typically low enough to be powered by a postage-stamp sized solar cell.

The other goal for the Claremont prototype was to extend the processor’s dynamic performance—from NTV to higher, more common computing voltages—while maintaining energy efficiency. Ruhl’s results showed that the technology works for ultra-low power applications that require only modest performance, from SoCs and graphics to sensor hubs and many-core CPUs. Reliable NTV operation was achieved using unique, IA-based circuit design techniques for logic and memories.

Further developments are needed to create standard NTV circuit libraries for common, low-voltage CAD methodologies. Apparently, such NTV designs require re-characterized constrained standard cell library to achieve such low corner voltages.

Rethinking standard approaches
Michael Parker, senior technical marketing manager at Altera, began a session at the recent Hot Chips conference by highlighting advances in the floating-point accuracy of FPGA devices. FPGAs are inherently better at fixed-point calculations, in part due to their routing architecture. Conversely, accurate floating-point calculations are dependent upon multiplier density for the extensive use of adders, multipliers, and other trigonometric functions. Often, these functions are pulled from libraries to form an inefficient multiplier implementation.

According to Parker, Altera took a different approach by using a new floating-point fused data path implementation instead of the existing IEEE-based method. The data path approach removes the typical normalization and de-normalization steps required in the multiplier-based IEEE representation. However, the data path approach only achieves this high floating point accuracy on smaller matrix functions (like FFTs), where low power GFlops per Watt performance and low latency—thanks to enough on-chip memory—are the primary requirements.

New materials
Robert Rogenmoser, senior vice president of product development and engineering at SuVolta, a semiconductor company focused on reducing CMOS power consumption, discussed ways to reduce transistor variability for low-power, high-performance chips.

Transistor variability at today’s lower process geometries comes from the typical sources of wafer yield variations and local transistor-to-transistor differences. Such variability has forced the semiconductor industry to look at new transistor technologies, especially for lower power chips.

What is the solution? Rogenmoser, in his Hot Chips presentation, discussed the pros and cons of three transistor alternatives: finFET or TriGate; fully-depleted silicon-on-Insulator (FD-SOI); and deeply-depleted channel (DDC) transistors. FinFET or TriGate technology promises high-drive current, but faces manufacturing, cost and intellectual property challenges. The latter point refers to IP changes required to support the new 3D transistor gate structures.

According to Rogenmoser, FD-SOI transistor technology enjoys the benefits of undoped channels, but lacks the capability of multi-voltages and a limited supply chain—a point that FD-SOI supporters say has already changed. Still, SuVolta favors deeply depleted channel transistors. This process offers straightforward insertions into bulk planar CMOS—especially from 90nm to 20nm and below. Equally important is the easy of migration of existing IP to the DDC process, he explained.

Rogenmoser concluded by explaining how DDC technology can bring back common low power tools to lower nodes, e.g., dynamic voltage and frequency scaling; body biasing and low-voltage operation.

Stacking die
Going vertical, or even horizontal through an interposer, is one of the most significant and physically observable architectural changes in the history of semiconductors. By shortening the wires and increasing the size of the data pipes, power can be reduced and performance can be increased significantly.

But how real is stacking? According to Sunil Patel, principal member of the technical staff for package technology at GlobalFoundries, it’s very real. “For 2.5D, 2014 will be a very interesting year,” said Patel. “By the end of 2013 the capability will be in place. Designs already are being considered and tried out. 3D mainly depends on memory standards and memory adoption. We’ll see a package-on-package and memory-on-logic configuration first. 3D memory has its own route, which is ahead of that. 3D memory on logic could be late 2014.”

He’s not alone in this belief. Steve Pateras, product marketing director for test at Mentor Graphics, said that from a tapeout point of view—the only window EDA companies have into architectural changes—2.5D already is happening. “We have customers taping out 2.5D. For 3D, we’re seeing design activity for memory on logic. Next year we’ll see some tapeouts.”

And Thorsten Matthias, business development director at EVGroup, said equipment is being sold to foundries right now to make this happen. “By the end of next year we believe all the major players will have production capacity for both 2.5D and 3D,” he said. “That’s probably not 20,000 to 50,000 wafers per month, but there will be production capacity at every player that wants to take a leading role. By the end of next year there will be a supply chain for 2.5D and 3D, although probably at a lower volume and for high-end products.”

By Ed Sperling
Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation.

LPHP: What comes next requires a lot of guesswork in the design, doesn’t it?
Moll: Yes, but until we have FPGAs that do everything we’re going to remain on a two- or three-year cycle. That means you’re going to be well ahead of anyone who’s going to be using it. In these big SoCs, the fact that they’re truly heterogeneous makes it hard to figure out what applications are going to be using it, which portions are going to be useful and which are going to be less useful, how the data is going to flow, what the power profile will look like. There are about five places in the chip where you can locate the display. When you’re turning your tablet around, Microsoft has one way of doing it, Android has chosen three different ways—and they all have different power profiles. All of the hardware underneath is scrambling to take advantage of these options.
Murphy: When you look at software, one of the key things that decides where you split things between hardware and software is virtualization. That has become a method to manage real-time versus regular Android behavior. The question is whether you do it all in the OS, or support it at least partially in the hardware. That will have implications for security and performance. There isn’t an easy answer of where you split things, even for the operating system functions.

LPHP: Who’s responsible when something goes wrong?
Murphy: If it’s Apple, that’s easy. For everyone else, it’s not.
Kulkarni: There were similar questions years ago with DRC (design rule checking). If you get a DRC error, who’s responsible? Is it the place-and-route tool that created it or the foundry. That used to be a very big headache for everyone, but it has dissipated over time. To solve this, standardization has to occur. There needs to be some kind of handoff with handshakes and protocols—and that includes hardware as well as software standards.
Moll: What we see from the middle of the chip is that standards are very important. And because chips are really assembled things, what they really need to do to make sure the pieces work together is to create standards at all levels. You need IP talking to the interconnect, and IP to IP. The verification is also really important. There is the portion where you make sure that everything is talking to everything else, that it’s spec compliant. There’s a big appetite for this because once people start assembling things they don’t want to verify everything, but they do want to verify that it all works together. On top of that, at the architectural level, there’s all the SystemC modeling where you want to make sure the performance is sufficient. People do prototyping and emulation, but that’s extremely slow. To make sure your chip will perform as well as you want it to, you need really good modeling capabilities. If you’re already prototyping and you have a big problem, it’s possible to reverse and do something entirely different. The hardware level standardization of all the blocks talking to each other is one thing. System-level verification is very important, and there are a few standards there that people are working on. And at a high level, there is the high-level modeling that you can run your software and performance on, and you may be able to drive power and other metrics that are very important from the system level. At these two levels, this is where the assembly happens and this is where the magic of making sure what you designed actually happens.

LPHP: Are we getting to the point where we have too many choices?
Kariat: Designs are getting more and more incremental. You can see that clearly in the Apple model. They rev their product and each time they change one thing. They move from one core to two cores. Then they add something else. You can’t rethink the whole system. Most of the market is operating on one-year cycles, so it has to be evolutionary. You can’t go back to the drawing board each time.

LPHP: But isn’t that easier for a company like Apple than a company trying to win a socket in a device?
Kariat: That’s why Apple and Samsung have a huge advantage. They are more vertically integrated. That’s also why you see more companies dropping out of that market.
Murphy: You can’t necessarily remove all risk, but you can reduce risk. That’s driven very much by de facto standards. If you have some level of signoff on IP, you don’t know all of this IP is clean and beyond reproach, but you have some level of confidence it is signed off from certain dimensions and that you can integrate it and not run into certain classes of problems. That’s a valuable thing that raises confidence and reduces insecurity that when you build something, it won’t work.
Buch: With a software program today, you don’t worry about your microprocessor having a bug. You just assume every layer under you works. In the hierarchy, if you go from the lowest level to the software verification, you need to be able to sign off without having to go deep down or you will never get anything done.
Kariat: A lot of the IP is already based on standards, so whenever you have a situation where the IP is supplied by someone else, there is a standard in place. Then there is verification IP, which allows someone to put in a model so they can simulate the system and they can see how the memory is used.
Moll: Some companies have lots of methodology around the tool flow and they may have a longer pipeline because of this, but they get to a higher level of quality and that works for the customers. And then there are guys who are hungrier and they shorten the cycle and hope the IP will be good quality and take more risk like assemble first or go to prototyping faster. There are shortcuts where you can dial your level of risk. If you want to get an edge over someone else and use the same IP, you have to shorten your schedule.

LPHP: One of the big issues facing the chip industry is double patterning. What impact does that have on the design side?
Kariat: Double patterning is definitely disruptive—how disruptive is not clear. It’s something designs need to take into account, but there are practices you can put in place where you don’t have to worry as much about it. There is a tradeoff. If you do more rigid prescriptive design rules you can get away from more of the complexity, but then you may lose density. It’s based on the system tradeoff. It’s a hump that people have to get over. New tools have to come in and people have to adapt to it. At this point, triple patterning isn’t immediately on the horizon.
Buch: There is some impact on placement, some impact on routing, but we are very solid with it. There are routers today that can deal with double patterning. I don’t think it’s going to bring the tools down to their knees.
Moll: At 28nm, when everyone wanted a high-performance processor the sticker shock was huge. It will be even higher in the future.

LPHP: It’s the cost of the design, the IP and the manufacturing, right?
Moll: Shrink was great because you used to get more transistors. Now it costs you the same for one triangle at 20nm.
Buch: It increases your mask cost. The lower layers will be a single pattern. Then when you go to the higher levels it will be double patterning. They are playing with this now. It’s not necessarily an EDA tool problem. It’s a business issue.
Kariat: People may do M1 to M4 as double patterning, and other layers single patterning.

LPHP: Verification has been a problem in complex design, and there is a lot more black-box verification going forward. Do we have sufficient coverage so we are confident what comes out it will work?
Moll: The reality is that nothing really works perfectly, but it works well enough. These days, if you have a huge chip you know there are hundreds of bugs buried in it. You work around that in software. More gates means more bugs.
Kariat: When we talk to customers, we hear the same discussion about quality and coverage for software.
Kulkarni: One of the problems we’re hearing involves the testbench itself. They’re either ATPG or APPG. What will exercise the chip or the subsystem for verification? That’s the first problem. There are huge testbenches. Tablet designs are now at a 1.1 billion-gate equivalent. It’s not even gaming GPUs, which are known to have that kind of complexity. That’s the next challenge I see.
Murphy: An interesting trend is assertion synthesis. As these things get bigger and bigger, writing dedicated testbenches to simulate is becoming non-viable. What you really want to do is run the applications on them, but then you want to have visibility into any strange things going on as those applications are run. The challenge is that it’s hard to write assertions. There’s a very specialized skill set to writing assertions. Is there a better way?

By Ed Sperling
Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation.

LPHP: With stacked die it’s no longer one company making an SoC. What does it mean for design, the tools and the ecosystem as a whole?
Kariat: There is definitely a trend toward multi-chip modules and 3D ICs. Some of it is because the economics make sense. You can design certain parts of the system at a much cheaper technology node and get much better yield. You can package them together and still fit them together in a form factor that works. That trend should show up more and more. Once you put them on the same process technology, you’re paying for the real estate so you want to use whatever you can, which is harder.
Kulkarni: Whether it’s 3D or 2.5D, in every device we use there are already multidimensional ICs. The customers we’re talking to are working with logic and memory, not logic on logic. So how do you manage all of this across the chip and through the interconnects? We see multi-domain analysis for the next generation of tools. The same tools will not be able to cut it. So to push the next technology node, if you have iTunes and Facebook and other applications, all of them take advantage of different circuits in a processor. The tasks have to be highly optimized. You don’t need to push to 20nm to listen to music. At the same time, if you are doing video streaming, you’re probably going to need the most advanced node. It will require a different profile in terms of high-speed buses, how things are integrated, and how they communicate with the outside world. People have to start looking at application-specific approaches where the software will drive how the hardware is architected as opposed to creating hardware and writing the software applications to that. As solution providers, we have to figure out how to deal with a higher and higher level of software control and see how we add value to that chain, from software architecture to hardware architecture to physical to the chip, the package, the subsystems, and so on. And then we need to look at EMI. As an industry, we have to go beyond the chip and look at a simulation-driven product design.
Buch: People are going down the wrong path with concern about tools. 3D is not necessarily a place-and-route and implementation issue. Some of that will be needed there, of course. The bigger issue, though, will be how you divide it up for power, for performance, and whether you use a different node or the same node Process estimates and power estimates are key. Once you figure out you want to do it this way, you can take any existing partitioning tool and, with some tweaks, make it work. I don’t see many people talking about TSV as a system-modeling problem.

LPHP: Aren’t the big problems how you integrate and physically put all of this stuff together?
Moll: In many ways, 3D is just a way of partitioning. The partitioning has existed for awhile. A particular subsystem may have its own power island, its own power supply, and it may be dark silicon most of the time. When you’re playing audio your video may be off. The GPU guys get to use the low Vt’s because they need megahertz while the other guys don’t. They already look like different chiplets. In some ways it is the same problem. It’s about integrating all of these things. Do we write software and ship drivers for all the pieces? In an old system, the guy doing the system could assemble it by buying a CPU from here, a GPU from there. Today you’ve got the power, the EMI, the software, the methodology for verification, the methodology for modeling, so when the chip gets taped out someone knows what it does. This is what we do. It’s a big integration issue from the stack of software all the way to the assembly of the IP and how it’s going to work.
Murphy: But how many degrees of freedom do you really need in the hardware? It’s going to cost $100 million or $200 million or $500 million to produce a chip. At some point it doesn’t make sense anymore. It’s simpler to solve the problem in software with better applications. If it’s going to cost $500 million to build it, it has to be able to target a multi-billion-dollar market.
Kariat: That’s already happening. If you look at the SoC’s that go into mobile phones, you have a system and you’re doing a lot of things in software. But one thing that we’ve seen over the last 12 months is a lot more companies jumping on the train to the next node than we have ever seen. We expected the microprocessor companies to be there and the FPGA companies to come right after them, because they need lots of area. Then you see the GPU companies, and then everyone else waits. That’s not what’s happening. We’re seeing the initial people come in, and then right behind them companies are moving in that you wouldn’t expect to be there this early. Power and integration drive that. The reason they’re all moving there is they all want to be in that little device, and that little device is packing in more functionality. Contrary to what we might think about not needing any more horsepower, there are a lot of applications we still can’t do on mobile devices. We can do more computing with lower power, but even if you look at something like voice recognition there is a lot more we can do with voice recognition that the hardware cannot enable.
Moll: The Internet is catching up. There’s a massive influx of people who want to participate in the whole mobility change, whether that’s cell phones, devices like tablets. Wireless infrastructure is a hot topic because everyone needs infrastructure. There’s also the cloud. This is creating a mini gold rush for these processors. They all want to participate and be competitive, and the only way to do this is with the latest and greatest from everybody.
Kulkarni: In the past people would say they had to meet timing performance. Now they say they have to meet the power budget. Many senior directors are saying they want the highest performance possible, but it has to meet a power budget. And that budget is for any range of applications.

LPHP: Isn’t it even beyond the chip? Aren’t we talking about the power budget for an entire device?
Kulkarni: Yes, it’s the system. It’s the subsystem and the system.
Murphy: HP has a program called Project Moonshot. It can collapse 100 blades down to a single blade. You can’t do that unless you can have a much lower power footprint.

LPHP: Does this happen faster at the data center/cloud level because they’re less price-sensitive?
Kulkarni: They started the trend that got transferred to the handheld mobile devices. Now it’s blending.
Murphy: It’s very much driven by the cloud. The whole social media revolution has created a huge market, but the infrastructure is not there today to handle all that traffic. It’s a different problem from the handsets. You don’t necessarily need a lot of compute power to handle Facebook traffic. You just need a lot of CPUs.

LPHP: There are lots of different types of software—software that controls things, embedded software, middleware, operating systems and applications. Who’s responsible for making sure that works well in the future?
Kariat: An abstraction layer is going to exist. The paradigm is to extract what you do on the hardware. At the application level you don’t want to deal with any of this stuff. People are going to higher and higher levels for databases and database transactions.
Kulkarni: Just like you measure hardware, with any application software there should be a power meter so any application you know the quality of that software. That kind of ‘Green’ stamp may become standard. A lot of people are talking about that—how to evaluate application software. Software is causing a lot of headaches. Even the big guys like Google and Microsoft are designing low-power software, doing dynamic scaling of that as if you were doing the same thing with the hardware. The software will be measured against the power it consumes. That’s a very important trend. It puts the software developers on the hook just like the hardware developers.
Buch: If you look at all the system-on-chips the question is how you address a system. You need all this stuff to boot up your processor core. Then you need all this programming. We have been looking at OpenCL applications where you can go from that to RTL, which can then by synthesized onto the FPGA. But you still need the ability to figure out what goes into software and what goes in hardware, starting with a high-level description. That’s a very interesting problem. In the coming few years we are going to move to an SoC platform where there will be some programmable logic where you draw your software differentiation and interconnects and program at a high level for a wide segment of the market.
Moll: To some extent, when you’re starting to design a chip, you’re designing for three years from now. If you’re designing for Android, you know what they’re going to do in six months or a year. But if you’re designing a chip for three years from now, what do you do? To actually create all of the hardware and the software the OS guys rely on you need to have a fairly educated guess about where things are going.

By Ed Sperling
Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation.

LPHP: Where will the pain points be going forward?
Kariat: 20nm is a big pain point already for technology, but it’s also a pain point for economic reasons. It looks like 14nm won’t be much more, and we don’t have any idea about 7nm. At 20nm, there are two sets of challenges. We’re introducing lots of new technologies that change the design flow. There is double patterning and local interconnects. The device variability will be significantly higher. Layout-dependent effects are going to be more of a problem. They’ve been a problem at 28nm, and they’ll be more of an issue at 20nm. We’re seeing a big different between the people who will build large SoCs and those who won’t. Each has a very different set of issues. There is a thinning going on here as companies drop into analog and specialized power.
Kulkarni: The pain points I’m seeing are from connecting the dots between chip, package and system. That involves power, signal, noise, EM, EMI, on-chip ESD. Driving all of that will be 3D IC. That’s what we’re losing sleep over.
Murphy: The big challenge we see is increasing complexity, and the need for physical awareness to be part of the architecture. If you look at what it takes to get gates down on silicon, you have to have a lot of configurable IP. That includes bus fabrics, the CPUs themselves, the cache memories. You think of this kind of stuff typically as an algorithm and performance problem, but it’s becoming a physical problem, as well. You can’t separate those anymore. You have to find ways to get physical insight—power, performance and area—while you’re developing the architecture. And that’s becoming more acute as the designs become bigger.
Buch: The biggest problem is going to be yield. The question at 20nm isn’t whether we’re moving to double patterning. It’s at what level do big designs yield. People who are going to 20nm are doing big GPUs and other chips. But getting those designs to yield at a good enough rate will be the big problem. We’ll get to 20nm; 14nm, who knows? How are we going to make the economics work? If you look at the design costs and the number of people and the design time and then you look at the yield, at what numbers does it all add up? People are dropping off on how fast they go to the next node. At 20nm there will be more drop-offs. Can TSMC keep up with Intel and Samsung? This will decide what kinds of designs get done. That is the biggest unknown at this point.
Moll: We’re seeing 28nm is already painful, for the usual reasons. The back end is really a front-end problem now. You have to figure out what you’re going to do on the back end when you’re architecting your chip—where your pads are, where your subsystems are, how you’re going to move things around, what it’s going to look like and how you’re going to connect things. What we’re seeing is instead of a rush to system on chip, it’s a rush to system in a corner of a chip. In a corner of a chip you can put a subsystem that is very substantial. There are caches and CPUs. What we see is a hierarchical approach being generalized to chip design. It used to be one person as the top-level architect. There is still a person in the middle, but that’s more of an integration person. And there are subsystems with entire teams developing large pieces. One thing that’s clear is you can’t do one of these chips all by yourself anymore. Maybe if you have something that’s very regular you can, but if you’re doing a mobility SoC with a huge catalog of IP, it’s impossible. The people who win will be the ones who apply their resources in a more intelligent fashion. They will figure out what differentiates them and shop for the rest.

LPHP: Is the solution just working with partners better, or is it rethinking chips entirely?
Vinod: The economics dictate we will see a few big companies reaching 14nm. We’ve been talking about SoCs for a long time. They’ve been systems, but they haven’t been put together like systems. Other pieces have to feed into it. That’s one of the dynamics changing there. We talk about IP a lot, but in reality there’s a long way before it’s put into practice.
Moll: In mobility, there’s a big land rush now. Everybody wants to have a mobility product. There are multiple companies getting into that market. At the same time, because it’s very competitive, the windows are getting shorter. Companies that used to do these chips in 24 months are now doing them in 18 months, and the ones doing it in 18 months are now doing it in 12. This is a double whammy. Not only are the chips more complicated, but they’re trying to shrink the development time as much as possible. This is where the hierarchical assembly process needs to be really well oiled.
Murphy: We all have gotten used to ARM being the CPU of choice, but Imagination has shown there is a market for star IP beyond just the core CPU. That’s a very popular GPU. It’s complex. It’s creating new challenges from an integration point of view. It’s a big hunk of logic, and you have to fit that big hunk of logic into something else. You can’t just say the floor plan is wide open. You have to carve out space for it. There may be an opportunity for other big subsystems like this. If you look at the market around servers, this is very hot. Oracle, AMD and Samsung are working on very small footprint servers that are multicore with a lot of bus fabric. Those could be subsystems themselves.
Kulkarni: All these things are about power, not just wireless applications. We see a spectrum of applications. If you have a disk controller running at 15 watts, they want to reduce it to 12 watts. We have customers at 65 watts to 70 watts in the server farm area, and they want to reduce it to 60 watts. What we find is everyone is facing power because power is noise and associated issues. It applies to IP within the context of the SoC around it, and multiple IPs, as well. How do you integrate that from power point of view? And with 3D ICs, each IC may have different thermal issues. There are more issues coming into the picture. There are a lot of issues with the package and the interposer and through-silicon vias. You cannot look at a single chip or even an SoC anymore. It’s multiple domains that impact each other.
Buch: And how are people going to make money out of all of this? TSMC has all these different processes for high performance, low power, and now there’s going to be just one at 20nm. With EDA tools, we’ve spent years trying to outperform everyone else, but the reality is Synopsys or Cadence tools can implement it. You need a platform these days. You’ll have an interconnect, and maybe an ARM core, and then how do you program all of this? Software is going to drive differentiation. That doesn’t mean problems don’t have to be solved. But I don’t seen anyone rising above the vendor or the IP noise and be able to say they’ve got something way better than everyone else. To solve this, someone will have to come up with a software idea, which is going to be the differentiator.

LPHP: How many tools from a company such as Altera are internally developed versus externally developed? And are the internally developed ones running out of steam?
Buch: I came over from Magma. Now I’m in charge of the tools, so I have a unique perspective. What you really need to do is bring in outside tools and have a bake-off and see which one is better for your needs. There are certain designs where tool ‘A’ is better than tool ‘B,’ but there are very few of those and you usually can get the job done either way. There are designs out there where you need to use hierarchy and break up the design, but the tools will get there. The question is how you make money as a tools vendor. Magma was seeing the number of customers going down, and if you don’t have a full portfolio you get squeezed. That commoditization is happening across the board everywhere.
Kariat: There is too much work to be done and it’s hard to make money because there are too few people who want to do the design. There are five people doing an SoC. But there are a lot more people in the other market who are doing a lot of IP design. Bosch is doing automotive chips. But they’re not in this domain at all. They’re at 2 microns. To go to 20nm and 14nm and serve a handful of companies that won’t use many of our tools, it’s a challenge.
Murphy: In the early days, IDMs developed their own CAD organizations. If this trend continues, they will have to develop their CAD organizations again. There are only a few companies that will need it.

By Ed Sperling
The move toward stacking of die has always been a series of disconnected pieces and vague promises for the future, but in the past few months the scenario has changed radically—and so has the commentary.

All three of the Big Three EDA vendors now have at least some of the pieces in place for 2.5D stacking and are working on a full 3D flow. Two of the biggest FPGA vendors, Altera and Xilinx, have rolled out 2.5D prototypes. The big foundries have developed processes and interposer technology. And IP vendors are beginning to talk about how IP will have to be characterized to work effectively in stacked-die configurations.

Unanimous vote of confidence
Possibly the most dramatic change has been at Synopsys, which has been vague about stacked die for the past couple of years as it tried to sort out where the issues were and where the opportunities will be.

“For some time, the situation has been very foggy,” said Marco Casale-Rossi, product marketing manager for implementation platforms at Synopsys. “We decided to let things settle to understand the main directions, and believe that over the last 18 months we have understood where mainstream will be—2.5D with an interposer. It will be a number of die, side by side, communicating through an interposer and with the outside world through a TSV.”

Synopsys has decided to focus in three areas: a complete solution for implementation and verification; an evolutionary 2.5D to 3D flow that builds on what already exists; and an R&D commitment with customers and research groups to solve whatever problems may come up in the future.

“Extraction will be very important,” Casale-Rossi said. “We need to take into account a number of new elements such as microbumps, TSVs and interposers. And historically, EDA tools have been designed to deal with one process technology at a time. Now we’ve got bricks manufactured using different process technologies and the rules are different depending on the die.”

EDA’s next big thing
Synopsys isn’t alone in trying to predict where the pain points and the opportunities will be. Both Cadence and Mentor Graphics threw their support behind stacked die over the past couple of years, and Cadence has been working on system-in-package since the beginning of the millennium. So far it appears that the opportunity is large enough and broad enough that there isn’t much overlap.

Cadence has built its 2.5D suite from its SiP tools, which were introduced in in 2007 at a time when the market was still focused on planar ASIC solutions. At that point, the company was divided over whether stacked die would really be an opportunity going forward. There is far less doubt these days that it was the right choice.

“The big question as we got into 3D was whether we build separate tools or use the same tools,” said Samta Bansal, senior product marketing for SoC Realization at Cadence. “We did need new layout tools because of the new electrical features—TSVs and microbumps. The analysis tools also have to be able to comprehend the new constraints, which are thermal and mechanical. And we needed new models and tools with respect to microbumps, and had to make sure the current tools understand the new dimensions.”

She said TSVs are similar to vias, but still different enough to require changes in the tools. And floor-planning requires understanding of placement in a stack to optimize behavior. But she noted that what customers discovered they really needed were tools for packaging.

“Customers that are developing 2.5D are looking at this one of two ways,” she said. “One is a package-driven flow, where the interposer is an extension of the package substrate. The other is an IC-driven flow, where as you go along you have more TSVs and more IC-centric routers. But for both of them, 3D stacking is a combination of digital, custom (analog/mixed signal) and the package.”

A 2.5D stack. Source: STMicroelectronics and Cadence

Mentor Graphics likewise has been extremely active in 2.5D, with a long-range view of 3D stacking, focusing in particular on both test and manufacturability.

“Several factors need to be addressed,” said Steve Pateras, product marketing director for Mentor Graphics’ silicon test products. “One is known good die. How good is the testing before you put chips in a package? Most times you test chips after they’re already in the package, but with 2.5D and 3D the yield goes down as you increase the number of die.”

A second issue involves I/O testing—or more accurately, the lack of testing—which takes on new meaning in a stacked die. In stacked die, it’s imperative to test the I/O before the die are packaged because many times it will not be testable after they’re already in the package.

Pateras said one of the approaches being talked about is wafer on wafer stacking to reduce costs, but that makes it particularly hard to test. He said the better approach is die-to-wafer stacking, using a base wafer with everything else stacked on top for greater control and better yield. But that also creates another problem.

“When you stack heterogeneous die in a stack, there is no standard for communication between the die,” he noted. “We’ve solved one problem, which is memory stacked on logic. But we need to develop a 3D test standard and standards for embedded self test.”

On the manufacturing side, Mentor has modified its DFM tools for 2.5D and 3D verification. And most experts believe existing ESL models can be relatively easily tweaked.

What’s still needed
It’s easy to forget that 2.5D and 3D are evolutionary steps with possibly game-changing impacts. While some EDA tools have always been offered well in advance of the mainstream, they are typically behind the chip design teams working at the leading edge of Moore’s Law. At 20nm and beyond, the cost of making chips has become so enormous that leading-edge companies are building upward. And as they do so, they are finding some pieces are missing that will need to be filled in.

“The first thing that’s missing involves the temperature issue,” said Ghislain Kaiser, CEO of Docea Power. “When you stack die together you’re putting more power into a package, whether it’s 2.5D or 3D. You have to manage that. Many times there is no dissipation problem, but you need to have tools to make sure. You need to be able to analyze the dynamic power profile, and right now it’s impossible to make a link between the software and dissipation when you run actual software on the chip. The best you can do is a simple profile.”

One of the great benefits of stacked die, in addition to not having to move analog designs to the next process node, is increased flexibility and options for designers. Teams can stack different memories in different places and they can move functionality from one die to another to improve performance or lower power or both.

“With that freedom you need to do more exploration,” said Kaiser. “But you may have too many degrees of freedom. You need to be able to optimize different chips along price, performance and power. And you need more accuracy. The gate-level tools are not 100% accurate.”

That’s easier said than done, however. There are no standards in the IP world that would allow an accurate comparison between one piece of IP and another. Frequently they are not even measured the same way by different vendors. Moreover, they can vary significantly with different usage scenarios.

That’s typically where standards fit in. Cadence’s Bansal said the foundation to enable 2.5D and 3D is clear, but there needs to be a seamless and consistent way to integrate digital, AMS and the package. “If the routing is not optimized, for example, you may end up with several layers of interposer. That will make the chip much more expensive.”

By John Blyler
Lattice Semiconductor’s proposed acquisition of FPGA start-up SiliconBlue Technologies for $62 million in cash is the latest signal that the smart-phone market may be showing signs of overcrowding.

While researchers are quick to point out the growth rates of smart phones sales versus computers, there also are an unprecedented number of companies vying for a stake of that market. Lattice’s push into adjacent markets is a hedge against that overcrowding.

Lattice until now has focused on the high end of the smart phone market. Silicon Blue targets mid-range players such as watch companies.

Doug Hunter, vice president of marketing at Lattice, said both companies occupy complementary spaces in the mobile consumer market. Silicon Blue offers a reduced feature set at lower power and with a one-time programmable (OTP) memory technology that it licensed exclusively from Kilopass. “This will allow us to go into customers with both a simpler and smaller or bigger and more fully featured suite of products,” explained Hunter.

By far the larger company, Lattice has more than $250 million in cash on the balance sheet with a good quality track record, said Hunter. The company also has a much wider distribution and sales network than start-up Silicon Blue, which should help win sales from customers that are reluctant to deal with a start-up company.

Still, Lattice has had its share of challenges in recent times, including numerous CEOs over the last six years and loss of market share to giants such as Xilinx and Altera. Hunter acknowledge these challenges, but highlight the company’s current strategy of finding niche to “differentiate, duck, bob and weave” against the two industry giants.

The acquisition of Silicon Blue fits that strategy. In addition to its mid-range handset sales, Silicon Blue recently won a design in an unusual ultra-lower power niche market. Watchmaker giant Citizen Watch selected SiliconBlue’s extremely low-power FPGA device for use in its new Eco-Drive Satellite Wave watch. Citizen claims that this is the world’s first solar-powered GPS-synchronized watch.

One key element in this selection by Citizen was the ultra low power of the company’s 8,000 FPGA logic cells, based on TSMCs 65nm low-power standard CMOS process. The other key factor was the tiny 4×5 mm footprint of the wafer-level chip package, where the ball-grid array (BGA) is placed directly on the wafer. This ensures a very thin package, essentially the same size as the dye.

Silicon Blue optimizes its designs for ultra-low power by using transistors with very fast switching speeds in critical areas of the design like clock trees. Additionally, their design makes use of the default “off” state inherent in FPGAs. “The network is only switched on when it is being used,” explained a company spokesman.

This move by Citizen to incorporate greater electronic functionality in its watches represents an interesting convergence between the worlds of traditionally mechanical-digital systems and fully electronic systems. Citizen’s Eco-Watch is a traditionally high-end timepiece that incorporates modern GPS technology. On the other side of the convergence are fully electronic systems like Apple’s Nano, a multimedia player with Wi-Fi connectivity that now incorporates a digital watch display.

By John Blyler
When designing for low power operation, engineers are constrained by the worst case (highest power) ratings for the silicon. But the power distribution characteristics of silicon can vary significantly from wafer lot to lot for the latest, lowest process geometry. How can designers deal with the worst case power ratings in their low power, high volume FPGAs designs?

First, let’s consider the process. To establish the power distribution range for their products, FPGA vendors start with a target yield. This yield provides the initial cost structure and allows them to publish numbers based on characterization over a statistically meaningful number of wafer lots, notes Christian Plante, director of marketing for low-power and mixed-signal FPGAs at Actel. “We characterize our silicon over many lots. Thus, it can take us a little while to put worst-case numbers (for the latest geometrics) into our software modeling tools.” The reason for this delay is that the latest process geometric nodes are less tamed than the older, higher, established nodes.

Characterizing worst-case conditions at higher nodes like 130nm isn’t a big problem. The manufacturing processes at these geometrics are well known. Thus, the power distribution curves are much tighter with less variation.

It’s the lower geometrics, like Xilinx’s and Altera’s 28nm processes, where the power distribution between wafer lots will be the most variant. And while this variation will tighten-up as the process matures, that will take some time.

Process variations during manufacturing also can worsen the affects of static power leakage, notes Michael Kendrick, product planning manager for Lattice Semiconductor. “As we move forward with geometries the voltage threshold decreases, which in turn causes static power leakage to increase, relative to dynamic power.” This results in a wider distribution of static power consumption over time – increasing the worst-case power constraints for FPGA designers.

Engineers are not without options. There are several techniques to mitigate the effects of static power leakage. For example, designers can be more careful on the mix of high-speed transistors used, since these transistors have higher leakage, says Kendrick. There are also process improvements that reduce leakage at 28nm.

The uncertainties of exact worst-case low-power conditions at lower geometrics, like 28nm, may give FPGA vendors of higher node chips an advantage. After all, the power distribution at higher nodes is more fully understood. Less variation in the power distribution of well-known, higher node geometrics should translate to less variant in the worse case power ranges.

But Actel’s Plante adds a note of caution, explaining that if the power distribution strays too far outside of customer expectations then the FPGA vendors can’t sell those chips—except to a customer that will accept the additional power consumption.

Further, FPGA vendors at the lower process nodes, like Xilinx’s new 28nm Virtex 7 and Altera’s Stratix V product lines, offer the lower power that is inherent with the move to smaller process geometry. Also, Xilinx emphasizes the power benefits of scalability with their new 28nm offerings. Both their lower-end, higher-volume and high-end, higher-performance FPGA families are built on the same underlying architecture, which may help mitigate the effects of wafer power distribution variations at the newer node.

The move to new process geometrics always brings new challenges. Fully understanding the variation of power distributions within the silicon is but one of those challenges that FPGA designers must understand when designing to worst-case power conditions.