By Ed Sperling
Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation.

LPHP: What are the main obstacles to lowering power in designs?
Clark: I take other people’s RTL and turn it into GDS II. In doing that, we use half a dozen different EDA tools. We really struggle with the unification of power intent and modeling. Getting accurate models consistent across tools and views is a huge struggle.
Venkatesh: Low power comes at a cost—typically performance. There should be a clear picture of tradeoffs. The other big piece in low power is that there is no clear link at various design stages. There is the architectural level, the TLM level, hardware and software, RTL and gate. You need good models at each stage, and you need to know at these stages what art the tradeoffs. So if you’re doing floating point computations, you need to know the cost of doing two digits or one digit. We don’t know what the difference in power consumption will be. Up to some point you should be able to have tradeoffs for power and also performance, and later at the RTL level onward you need to know how far off you are in terms of correlation to silicon. Power modeling associated with power measurement at each stage is very important.
Wang: From my perspective there are no obstacles. It depends on where you want to go. There are people pushing the power envelope today that no one could even imagine 10 years ago. Human nature will push that even lower, which will require innovation in process, tools, and design circuit techniques. All of these elements need to come together.
Trihy: There are three parts of this. One is the enablement from EDA vendors, and we see a lot of that available today. There are CPF and UPF. Liberty has many techniques for modeling different kinds of cells. Then there is the circuit designer. We will begin to see more circuit innovation. One example is resonant clocking. As the frequencies increase above 4GHz, it makes more sense to put clock meshes on the chips. You’ll see much more focus on accurate inductor design. There will be new techniques. As a foundry, we have to provide a value for customers to migrate to our next offering. There you’ll see the advent of the finFET. Today we offer a 20nm process. We call it “finification.” If you “finify” a design you can see a 40% to 50% reduction in power. All of these are moving in tandem and they’re all achievable.

LPHP: Is power the biggest problem we face going forward?
Trihy: It’s not problem No. 1. You’ll continue to see power, performance and area. We trade them off against each other. At the foundry we build flows for maximum performance, minimum area and best power. They’re so interrelated you can’t just pull one out.
Wang: I have a different opinion. Power is more of a problem than the others. In the last 10 to 20 years, there has been a lot of effort devoted to performance, but we have left a lot of margin on the power side. Why do we keep Vdd at 1 volt? There’s no point. You can drop Vdd to 0.3 or 0.4. People need a safer way to do circuit design. We have a lot of room for improvement there. But looking into the future of platform-based design, we are squeezing more and more functionality on silicon. There is a limit to how many cores you can use. We cannot go beyond a certain frequency—about 2 to 2.3 GHz. Gary Smith predicts that for embedded processors it will stop at 1GHz, with additional throughput from multicore architectures. The reality is that we are reaching the limit of performance. As a result, power will be a higher priority going forward.
Venkatesh: Power management is the No. 1 problem. It’s more related to energy, which is the biggest challenge. There are so many techniques to deliver on performance, but each time power is a problem. In mobile computing, there is a lot of idle time. You can deliver the performance with many cores, but you hit the power budget right away. New techniques are being considered for performance. One that’s being worked on at the University of Pennsylvania is called computational sprinting. It’s based on dark silicon, but when you need enormous performance they turn on all these cores. But they don’t stay on too long because that generates too much heat.
Clark: Power is a big deal, but it’s not very visible to the people implementing the functions. They leave it for the people implementing the structure. They figure, ‘You’ll turn off the right island at the right time.’ It’s a division of labor problem. A lot of our cell coders don’t think about power. It is a challenge, and it hits everything. It affects design for manufacturing, design for test, implementation, all the EDA tools. It touches everything you do. Maybe getting to the lowest power possible isn’t critical. But having a strategic power implementation that works and is testable and still performs the function you intended is a huge challenge.

LPHP: Is all the low-hanging fruit gone?
Clark: No.
Venkatesh: There are a lot of great techniques used by mobile companies that are not easily used by other companies, such as the creation of power domains, voltage scaling, DVFS.

LPHP: But is that really low-hanging fruit?
Venkatesh: It’s at least well understood by the mobile companies. You have to make it more commonplace.
Clark: There’s a small fraction of the chips being manufactured that really are bleeding edge on power management and power architectures. Everyone else thinks, ‘When it gets easy enough we’ll do it.’ The techniques aren’t new, but getting the broad adoption of it is still low-hanging fruit.
Wang: It depends on where you want to go. If you can sell a chip for $1 at 1 watt, why do you need to get it down to 0.8 watts? Economically it doesn’t make sense. The architect decides how the power goes, but you have to sign off on it. The cost of fixing power at an early stage is much lower than fixing it at a later stage. My iPhone is faster than I need. How fast it refreshes depends on my WiFi link and 3G or 4G, not the computation. Over the next decade there will be more and more integration and mobility. In China they have a new term called T2T. It’s thing-to-thing. It’s the same concept as the Internet of Things. All of those push the envelope of low power. People will find low-hanging fruit when they need to find it.
Clark: We have a lot of pressure for time to market. One of our big events is CES. We have to tape out two months ago to demo something at CES. What falls off is power because it’s not necessary for the chip to function.

LPHP: Does power become a focus of attention at the foundry level?
Trihy: Our real focus is yield, but what does surface is less about power directly and more about margin. We rarely hear about customers directly asking about their power spec, but we do get customers asking for help meeting timing closure.
Clark: It will still work if it uses more power. It will still function in the TV or the phone, even though you might not get your ‘green’ sticker.
Venkatesh: We’ve been hearing some companies dropping functionality to keep within the power budget.
Clark: We don’t always know what’s outside the power budget, though. There’s a measurement problem, too. We drop the clock frequency if there’s a problem.
Wang: Nvidia has a very fancy liquid fan that has save their design. For that application it works.
Clark: If you can plug it into the wall, you have a lot more leeway.

LPHP: What does die stacking do to this equation?
Venkatesh: There will be thermal issues. You can manage timing and placement reasonably well, but the thermal problem is acute. And power and thermal go hand in hand. As a result, your floorplan has to change.

Low Power-High Performance Engineering talks about problems in low-power design with Richard Trihy of GlobalFoundries, Leah Clark of Broadcom, Qi Wang of Cadence and Venki Venkatesh of Atrenta.

By John Blyler & Ed Sperling
For the past couple of process nodes chipmakers have been developing power-saving features that have been largely ignored by OEMs. That’s beginning to change.

The need to do more and faster processing within the same or smaller power budget is forcing significant architectural changes, more efficient software, and new materials into the equation. They are showing up in some of the latest announcements and presentations from companies across the semiconductor industry.

Architectural leaps
David “Dadi” Perlmutter, in his keynote address at the Intel Developer Forum this week, hinted at some architectural changes that will help pave the way for new voice and gesture-recognition interfaces. One involves near-threshold voltage scaling, something he referred to as “versatile performance.” As he put it, “if the platform is not warm enough, you scale down.”

To get to the next steps, Intel will need to add a number of architectural changes. The first will be rolled out next year with a 22nm processor, code-named Haswell, that includes its TriGate or finFET technology. That will be followed by a 14nm chip, which Intel reportedly is already testing.

Intel has been working with a variety of materials, including fully depleted SOI, and it has been experimenting with various gate structures and stacking approaches. But which ones ultimately get used depend on when it becomes economically required to change its processes and manufacturing. The company may buy some time just by using bulk CMOS combined with EUV lithography and 450mm wafer technology, in which it has invested heavily over the past few months. Bigger wafers and commercially viable EUV could well pave the way for advances at the next couple of process nodes.

In a speech prior to IDF, Intel Labs’ Gregory Ruhl talked about the energy benefits of Near Threshold Voltage (NTV) computing using Intel’s IA-32, 32nm CMOS processor technology. The so-called “Claremont” prototype chip relies on an ultra-low voltage circuit to greatly reduce energy consumption. This class of processor operates close to the transistor’s turn-on or threshold voltage—hence the NTV name. Threshold voltages vary with transistor type, but are typically low enough to be powered by a postage-stamp sized solar cell.

The other goal for the Claremont prototype was to extend the processor’s dynamic performance—from NTV to higher, more common computing voltages—while maintaining energy efficiency. Ruhl’s results showed that the technology works for ultra-low power applications that require only modest performance, from SoCs and graphics to sensor hubs and many-core CPUs. Reliable NTV operation was achieved using unique, IA-based circuit design techniques for logic and memories.

Further developments are needed to create standard NTV circuit libraries for common, low-voltage CAD methodologies. Apparently, such NTV designs require re-characterized constrained standard cell library to achieve such low corner voltages.

Rethinking standard approaches
Michael Parker, senior technical marketing manager at Altera, began a session at the recent Hot Chips conference by highlighting advances in the floating-point accuracy of FPGA devices. FPGAs are inherently better at fixed-point calculations, in part due to their routing architecture. Conversely, accurate floating-point calculations are dependent upon multiplier density for the extensive use of adders, multipliers, and other trigonometric functions. Often, these functions are pulled from libraries to form an inefficient multiplier implementation.

According to Parker, Altera took a different approach by using a new floating-point fused data path implementation instead of the existing IEEE-based method. The data path approach removes the typical normalization and de-normalization steps required in the multiplier-based IEEE representation. However, the data path approach only achieves this high floating point accuracy on smaller matrix functions (like FFTs), where low power GFlops per Watt performance and low latency—thanks to enough on-chip memory—are the primary requirements.

New materials
Robert Rogenmoser, senior vice president of product development and engineering at SuVolta, a semiconductor company focused on reducing CMOS power consumption, discussed ways to reduce transistor variability for low-power, high-performance chips.

Transistor variability at today’s lower process geometries comes from the typical sources of wafer yield variations and local transistor-to-transistor differences. Such variability has forced the semiconductor industry to look at new transistor technologies, especially for lower power chips.

What is the solution? Rogenmoser, in his Hot Chips presentation, discussed the pros and cons of three transistor alternatives: finFET or TriGate; fully-depleted silicon-on-Insulator (FD-SOI); and deeply-depleted channel (DDC) transistors. FinFET or TriGate technology promises high-drive current, but faces manufacturing, cost and intellectual property challenges. The latter point refers to IP changes required to support the new 3D transistor gate structures.

According to Rogenmoser, FD-SOI transistor technology enjoys the benefits of undoped channels, but lacks the capability of multi-voltages and a limited supply chain—a point that FD-SOI supporters say has already changed. Still, SuVolta favors deeply depleted channel transistors. This process offers straightforward insertions into bulk planar CMOS—especially from 90nm to 20nm and below. Equally important is the easy of migration of existing IP to the DDC process, he explained.

Rogenmoser concluded by explaining how DDC technology can bring back common low power tools to lower nodes, e.g., dynamic voltage and frequency scaling; body biasing and low-voltage operation.

Stacking die
Going vertical, or even horizontal through an interposer, is one of the most significant and physically observable architectural changes in the history of semiconductors. By shortening the wires and increasing the size of the data pipes, power can be reduced and performance can be increased significantly.

But how real is stacking? According to Sunil Patel, principal member of the technical staff for package technology at GlobalFoundries, it’s very real. “For 2.5D, 2014 will be a very interesting year,” said Patel. “By the end of 2013 the capability will be in place. Designs already are being considered and tried out. 3D mainly depends on memory standards and memory adoption. We’ll see a package-on-package and memory-on-logic configuration first. 3D memory has its own route, which is ahead of that. 3D memory on logic could be late 2014.”

He’s not alone in this belief. Steve Pateras, product marketing director for test at Mentor Graphics, said that from a tapeout point of view—the only window EDA companies have into architectural changes—2.5D already is happening. “We have customers taping out 2.5D. For 3D, we’re seeing design activity for memory on logic. Next year we’ll see some tapeouts.”

And Thorsten Matthias, business development director at EVGroup, said equipment is being sold to foundries right now to make this happen. “By the end of next year we believe all the major players will have production capacity for both 2.5D and 3D,” he said. “That’s probably not 20,000 to 50,000 wafers per month, but there will be production capacity at every player that wants to take a leading role. By the end of next year there will be a supply chain for 2.5D and 3D, although probably at a lower volume and for high-end products.”

By Ann Steffora Mutschler
With the complexity of getting 28 and 20nm designs to reach desired yields with the desired power and performance on the shoulders of design teams, advanced power management techniques are a must. Sub-clock power gating, clock power gate structures, adaptive body bias and other techniques are making it possible.

Sub-Clock Power Gating
Far from a new technique, power gating essentially stops all the current flowing into the system because when the electronic device is not being used, it helps to reduce the ideal mode power or the leakage current. “Essentially we turn off the switch so that there is a break or discontinuity in the whole circuit. We usually do that in an ideal mode because in the operational mode we want the devices to be working,” explained Aveek Sarkar, vice president of product engineering and customer support at Apache Design.

“Then, when it comes to sub-clock power gating, within a clock period, let’s say you are running a 100 MHz clock, it’s a 10 nanosecond clock period. But within that 10 nanoseconds we are actually doing logic operations during all of that period because devices tend to be so much faster nowadays. Most of the operation may end up finishing within one nanosecond or so. The remaining nine nanoseconds you pretty much have a dead period before the next set of activity comes along. Can we shut off the power coming into the device for that nine nanoseconds? If you do that and do it efficiently we can even get 25X power efficiency,” he continued.

Clock Power Gate Structures
Clive Bittlestone, a Texas Instruments fellow, noted during a panel session at the Design Automation Conference last month that in advanced power management, clock power gate structures are useful.

Adaptive Body Biasing
Adaptive body biasing is a technique that is, “becoming pretty interesting especially if you look at FD-SOI (fully depleted silicon-on-insulator),” Sarkar noted. Last month, STMicroelectronics announced it would use GlobalFoundries as an additional source for its 28nm and 20nm FD-SOI process.

He pointed to the comment by Philippe Magarshack, ST’s group vice president for technology R&D, in which he said this can be used either for the high-performance mode or the low-leakage-current mode by biasing the substrate dynamically, meaning that some parts of the design can be running at a high frequency mode and simultaneously part of the design can be working in the low leakage mode. “That’s definitely one of the directions we see. Obviously it introduces a lot of additional complexity.”

On-Chip Regulators
Yet another technique is the use of on-chip regulators. With advanced power management, one of the common techniques used is near-threshold computing, which is to reduce the supply voltage that is significantly close to the threshold voltage but also means that the noise margin goes down significantly.

“Let’s say what threshold essentially means is that if you reach 300 millivolts, the device starts to operate in another logic state, but if your supply voltage is only 400 millivolts then any small amount of derivation can cause a device to change state. When we had the supply voltage at 1 volt, we had a large amount of noise margin—400 or 500 millivolts—that definitely does not exist, so we have to be more careful about modeling and predicting noise in the circuit and make sure that the noise that’s being generated does not have a harmful effect on the end device especially because the noise margins are so much more compressed,” Sarkar explained.

The primary reason to go to these low supply voltages is to reduce power. “If you look at a supply voltage of 1 volt versus 700 millivolts—just because you go to 700 millivolts do you reduce your power consumption by half because it’s V2 and you automatically reduce it by half? In order to enable this type of near-threshold computing architecture you need to use more complex power supply devices; the board level regulator does not suffice. Dadi Perlmutter from Intel talked about this in his ISSCC keynote. Because we cannot manage the noise on the board and the package that carefully they are moving to using on-chip voltage regulators—they can reduce the supply voltage significantly. The other benefit with on-chip regulators is that dynamic voltage scaling is much more possible,” he said.

However, there are issues with using on-chip regulators because unlike off-chip regulators they have limited capabilities: if current is drawn too fast, it may not be able to respond and supply the voltage quickly. To account for this, some tools allow for the creation of models of this on-chip regulator and use this for dynamic voltage drop analysis to predict what the behavior of the circuit is going to be in a real-world scenario.

At the end of the day, the biggest bang for the buck is always making architecture changes high up in the level of abstraction, said Nikhil Sharma, vice president of engineering at Calypto. “That’s there no matter what the geometry is. Based on the actual gate level and transistor level tricks you can get some power savings but our hope is that we can convince people to make changes and use power technologies to help facilitate or automate some of tough decisions that they need to make at hopefully the architectural level or the RTL.”

Is DAC really a design automation conference, or has it shifted to a design enablement conference due to rising complexity breaking down traditional barriers and silos? Low Power High Performance Engineering talks with Atrenta CTO Bernard Murphy about the changes.

By Ed Sperling
Standards groups are beginning to look at power and other physical effects much more seriously in the wake of the dueling power formats—UPF and CPF—that have caused angst across the design industry.

To put it in perspective, when CPF and UPF were first introduced power was something of an afterthought in design. At 65nm it ceased to be something that could be dealt with later in the design process, and at 28nm it has become an essential part of the architecture. But as battery life, mobility, and energy costs even for plugged-in devices become overriding concerns, power now needs to be considered at full system level, which could mean everything from a rack of servers to an automobile.

Much of this is being driven from the chip level, and in the software that manages chips and interactions between chips. There are at least a half dozen new standards efforts under way or on the drawing board. Most heavily leverage the expertise of chipmaker and where they have encountered or expect to encounter pain in designs, most notably in stacked die or in planar SoCs below 20nm, or from tools vendors that have gained expertise in a specific area.

Si2 currently has one standard in legal review for system-level power modeling. The standard is called “atomic” power modeling, based on the assumption that the model cannot be broken down into smaller pieces, although it can be used at various levels of abstraction.

Also in the works is a standard for co-design, which is one of the most difficult challenges facing design today. While hardware engineers are well versed in how to build an energy-efficient chip, that engineering effort can be wasted if the software running on an SoC isn’t energy-efficient, as well.

“The first step is to get there with the architectural ESL level,” said Steve Schulz, president and CEO of Si2. “Then, we will look at how the software runs and develop a bridge. You will never get the software community to adopt the hardware approach to design. That community is 20 to 30 times larger than hardware engineers and they have their own tool flows. We have to think about a minimally intrusive solution. We’ve called it a bridge to the software world, and if it’s not intrusive then the software teams will use it. Most of them will never understand concurrency and how to get to a GDS II stream, but there are characteristics that are reasonable proxies of the details. You don’t simulate all the code, but you do generate enough discrete choices so everyone can get on the right track for power.”

A first step in that direction is finding data objects that can be passed back and forth between the software and hardware teams. From there a power model will need to be created across both. The power-flow group within Si2 has been reactivated to develop a source for the power model. “The focus this year will be hardware,” said Schulz. “In 2013 we will turn our attention to understand the data objects stored.”

That puts the likely adoption timeframe a of a co-design framework for power in the 2015 time frame—roughly at the 14nm process node and at a time when 2.5D stacking is expected to be mainstream and 3D stacking will become more commonplace.

Stacking effects
“There are two new requirements for design,” said Andrew Yang, president of Apache Design. “The first is a 3D IC flow. The second is an RTL-to-gate power methodology.”

Included in the 3D requirements is the need for multi-die thermal and stress analysis. Yang said the key is the amount of current a design can sustain without failure over time, and it gets worse at advanced nodes and sometimes in stacked configurations because wire handling capability is decreasing, power density is increasing, and electromigration is increasing.

3D IC thermal stress analysis. Memory die is impacted by power distribution of logic die. Source: Apache Design.

“This can be a safety issue,” he said. “You need to make sure the metal topology is handled correctly. Electromigration is affected by heat. The hotter it gets, the less current a metal wire can sustain. The electromigration rules are increasing, which is why GlobalFoundries, Intel and TSMC are all coming up with complex electromigration rules.”

Front to back, back to front
Being able to get a chip out the door at all is a challenge, which is why there are more standards being dictated from the foundries these days. In addition to process variation, continually shrinking geometries is making it harder to obtain adequate yields as quickly as in the past. That has led to more rules for place and route, test, IP, and layered across all of those is power.

“We’re seeing it in the available sizes, speeds, memory and logic cell sizes,” said Chris Rowen, CTO at Tensilica. “That’s what we target—area, power and process compatibilities. Whether that’s stacked or conventional die is affected only subtly. But with die stacking you will see significantly higher bandwidth and less latency, which will have an effect on modeling of the system. It’s not a qualitative change, but it is a quantitative change. It won’t change how one DSP communicates with another, but it will change how DSPs communicate with memory.”

How much of that will be standards promoted by standards bodies versus de facto standards from the largest foundries remains is unknown. Also missing are good open standards for on-chip debug and trace, said Rowen.

ESL standards
One of the most glaring holes in all of this is at the ESL level, where standards for power models are non-existent. While this isn’t a big problem in a single vertically integrated company, it’s a huge problem in a disaggregated supply chain where various companies work on designs—something that will become even more pronounced in stacked die where subsystems at different process geometries need to be integrated with other subsystems.

“What’s missing is something that allows companies to exchange power models, especially for IP-based designs” said Ghislain Kaiser, CEO of Docea Power. “In an ideal flow you would be able to take the IP from the IP suppliers and put together a power model and assess the power impact on the underlying hardware. But you also need to have interoperability between suppliers and customers that goes beyond the semiconductor level. It has to be optimized at each level—the SoC, the chip set, the PCB and above. So there won’t be only one number.”

The accuracy of those power models also will shift throughout the design. At the beginning a model may be only 40% accurate, but at the end it may need to be accurate to plus or minus 5%, Kaiser said.

Other pieces are missing, as well. Kiran Vittal, senior director of product marketing at Atrenta. “Right now, when a designer uses memory they don’t realize the code they are writing is not optimized for power. When you read memory you get a redundant read. The controller code isn’t optimized for memory. And all of that has to be networked, because you may have as many as 2,000 memories in a design. If you do it right you can save about 20% of the memories and the power needed to run them.”

To show just how bad this can get, a large systems house was designing a chip was required to give an early indication of its power budget to the OEM. The OEM used that estimate for calculating its own power budget and came up with a spreadsheet that represented the total design. The problem was that the spreadsheet ultimately was off by 100% in its power estimate, which in turn caused problems with the final device and greatly increased the amount of time it took to successfully bring a product to market.

“A lot of the ESL tools today know performance and area, but they don’t have a clue about power,” said Vittal. “This is fertile ground for innovation.”

By Pallab Chatterjee
FinFETs, stacked die, heterogeneous interposers, TSVs, 450mm wafers, new interconnects and everything with MEMs and sensors is what the last few weeks have brought. A number of major announcements, technology releases, conference updates have identified these technologies as the future of IC design.

At ISQED, Robert Geer, chief academic officer at the College of Nanoscale Science and Engineering in Albany, N.Y., discussed nanotechnology programs while highlighting the construction of a new building dedicated to 450mm wafer fab development. This new fab will support R&D for equipment, devices, and processes for the wafers that just a few years ago fell under the heading of, “most likely not going to happen.” The facility will work on lithography, front end of line (FEOL) and back end of line (BEOL), as well as adjustments to and planning for the logistics for managing these massive and very heavy wafers. This is being done concurrently with further development into the single-digit nanometer process and device technologies. These new flows and processes target devices with operating voltages of less than 0.8v, breaking the 1 volt threshold that has been dominant for more than 50 years.

Adding into to how these new processes will perform, the Common Platform Group (GlobalFoundries, IBM and Samsung) presented 20nm high-k/metal gate flows and identified this is the end of the line for Planar CMOS. Beyond 20nm, the next-generation devices will be FinFETs, with more exotic devices to follow below 10nm. Better control of leakage, as well as improved low-power performance, are due in part to these new devices not having a diffused source/drain in the bulk or epi material, which can serious impact secondary current paths. However, the devices do raise several new concerns, not the smallest of which is the device description. Instead of just W and L, designers now will have to add Z. This impacts simulators, netlists, and physical build/verification of the designs.

While most of the talk has been on process capability, there also is a lot of attention being focused on changes in IP and design methodologies. A consistent theme in these discussions is that power is the No. 1 design constraint and drives even functionality for the definition of new designs. Power, and the new soft metric of performance per watt, are the basis for these new $100M design development projects. IBM and Samsung executives noted that the economics of these new designs have changed significantly.

The basis of power as the overall constraint has now brought the impact of packaging and other modules into the design process. Local thermal balance, power distribution, bonding methods, stacked die, and signal interconnect to adjacent devices are now required parts of the initial SoC design.

MEMS is a case in point. The key issue MEMS developers wrestle with are power and accuracy, rather than speed. Most of the MEMS systems have 16-to-30-bit accuracy on the sensor element, but the challenge is getting these signals to the data-processing electronics with as little disruption using as little power as possible. Noisy interfaces consume power and reduce the signal integrity and accuracy of the main datapath. As the Internet of Things progresses to have sensors in everything, the power shifts from the logic processing section to the RF and communication circuitry. These blocks have to be balanced with the reporting rate, which operates the radios, and when the low power data is being collected. The majority of the systems on the Internet of Things are multi-die devices.

TSMC joined the fray with its new interposer announcement. It was not clear by industry naming convention (2.5D, 2.75D, or 3D) what the technique should be called, but it brought major technical advances toward the stacked memory on logic design methodology and the major performance/watt improvement over other technologies. This once again, brings power as the driver to the forefront.

By Ed Sperling
Low-Power Engineering sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; Vishal Kapoor, vice president of marketing for SoC realization at Cadence; Naveed Sherwani, CEO of Open-Silicon; John Heinlein, vice president of marketing at ARM; and Jeff Lukanc, director of engineering at IDT. What follows are excerpts of that conversation, which was held in front of a live audience at the Global Technology Conference in Santa Clara, Calif.

LPE: Is it harder to sell EDA tools for older nodes?
Heinlein: On one hand, the EDA requirements of the industry are evolving quickly. There’s one challenge where people have older tools, and you have to do new IP based on older flows. And then you have people wanting to use new tools on older nodes. They may want to use things like CPF. So we have this schizophrenia and we have to support that.
Kapoor: EDA is about tools, IP and services, and the reason the design components start to come in is that when you get to new nodes or existing nodes, you have to go broader than just tooling.
Sherwani: If you are developing tools for 14nm you are dealing with FinFETs and a lot of physical effects. But at 0.18 (microns) the issue is how to make one or two designers very efficient. We need to hire operations business people who have nothing to do with design in order to change that. EDA companies are very much focused on physics and getting to 20nm and 14nm. They still don’t have the mindset toward finishing a 0.18 design in one day. Is it possible to put together a flow that can be done by only one guy? In addition, many designs are derivative designs. Companies may want to add DDR3 to an existing design. The headcount and mindset required is very different.
Kapoor: We were joking before this panel that somewhere between the 34th and 43rd minute if I’m on a panel with Naveed he’s going to ask for free tools. With all due respect, that’s not a business we’re in. But in our core EDA business, we spend a lot of time on engineering efficiency. You will see a set of capabilities from Cadence that will address that. But if you can get an engineer to do a 180nm in a day, we should spin off a business.
Sherwani: The tools are focused on efficiency, but not on whether you can do designs in a day. If you can do a design in a day, you still have to verify that.
Ng: The point Naveed is raising is a cost issue. Whether it’s at the leading edge or older nodes, cost is in the purview of whether it even makes sense to do the design. Years ago when I was at Cadence we had a seven-day design goal. EDA hasn’t always looked at driving cost and efficiency.
Kapoor: First and foremost, EDA is about density and automation. The second part is that you have to figure out how the economics of the whole industry work. If at 40nm we spend $600 million putting together technology, to have anyone design at that node you need sufficient volume to get an acceptable return. And at 28nm it’s $1 billion and at 20nm $1.5 billion. You have to recognize that everyone can’t have an apps processor. That’s not going to happen. Just like there are limits to technology, there are limits to economics. If that’s what it will take us to put into it as part of the broader industry, that’s what we’re going to have to bear.
Ng: Do you think EDA has been driven to the same level of efficiency as other parts of the supply chain?
Kapoor: That’s not a fair question and here’s why: The way the business model for the tools piece works is different than for the semiconductor manufacturing. In the long term, if we bring on additional services will we look to be more in line with other parts of the supply chain, including Naveed’s business? Absolutely.

LPE: If power was not an issue at 180nm in the past, why is it such a big issue now?
Heinlein: Because the bar always moves. People are looking at applications that require low power much more than before. We also need to have power management ICs alongside other chips. And there’s a question of using the right hammer to solve a problem. The bar is different than it used to be.
Lukanc: The mix of things you put in a chip is different. There are mixed signal and power management. You can get a 40-volt PCB process at 0.25 microns. Now 30-volt processes are available at 0.13. You can mix things together and keep mask costs relatively low. Time to market is shorter, investment is lower and it requires fewer people.

LPE: What does the ecosystem look like with more foundries at older nodes?
Sherwani: These are not like TSMC or GlobalFoundries. They have their own IP houses or in-house IP.
Heinlein: That’s correct. These are companies that are very comfortable in their niche markets. That said, we are starting to witness sea changes in areas such as embedded microcontrollers, driven by the so-called Internet of things. That’s going to drive people to put microcontrollers and processors in places where they’ve never been before. Enabling modern software development and EDA development allows you to do more.
Kapoor: If you’re talking about a transducer or something like that, you’ll have to integrate the increasing analog and mixed signal capability with the digital capability. A mature node makes perfect sense. What you have to learn is what you need from the EDA side all the way to the manufacturing side.

By Ed Sperling
Semiconductor design always has been about solving technology issues one node at a time, often in the face of a perpetual barrage of looming problems. In fact, if there is any change at all, it’s in the number of threats that have to be solved now at each node, most of them driven by ever-increasing density and the laws of physics.

Stacking die holds the promise of becoming something of a game changer because it can solve multiple issues at once—power, performance, physical effects such as noise and crosstalk—while creating its own issues such as who’s responsible when two known good die don’t work in a package.

But the surprise among companies working with this packaging approach is that it’s harder to remove the heat from stacked die than anyone initially thought. The generally accepted premise that silicon is a good conductor of heat is true, but apparently not true enough. Early tests show that 3D stacks are showing some limits for through-silicon vias.

“What we found is that you have about a 7 to 10 watt maximum for through-silicon vias using current technology,” said Greg Bartlett, senior vice president of technology and integration engineering at GlobalFoundries. “After that you have to go to an interposer.”

This is somewhat counterintuitive, because most engineers have always assumed that 3D stacking would be the successor to 2.5D stacks. Unless something is done to change the technology, it may be the other way around. This is good news in one sense. It’s cheaper and easier to work with an interposer, which contains TSVs on a separate piece of silicon, than with TSVs running directly through stacked layers of thinner chips. There is less stress to deal with from drilling through a layer of silicon, and yield is higher if those TSVs are run through a thicker piece of silicon.

“The big problem now is that with a dense TSV the heat is trapped,” said Dian Yang, senior vice president of product management at Apache. “You have to use metal to dissipate the heat. People didn’t know the power density would be so high, and that has causes thermal issues that are much more severe.”

In 2.5D stacking, the tradeoff is the footprint. A 3D stack is much smaller and can fit into smaller spaces, which is why it has been of particular interest to companies such as Broadcom and Qualcomm.

It’s not the TSV technology itself that is causing problems. It’s the location of the TSVs. There are still places where TSVs work extremely well, such as inside of interposers and in stacked memory configurations. Memory is particularly attractive because it doesn’t generate heat anywhere near the level of logic. Micron and Samsung are both developing stacked memory configurations using TSVs and claim faster performance, higher density and lower power. This kind of memory can be used in a 2.5D as well as a 3D stack.

Other considerations are under way, as well, such as using different substrate materials using different cooling methods, such as microfluidics. But there will either have to be a compelling technology reason, which so far has not been proven, or a major ability to reduce the cost of these approaches before this kind of technology hits the mainstream. Until then, it’s anyone’s guess whether and for how long a pure 3D stacking approach will be successful.

By Ed Sperling
Low-Power Engineering sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; Vishal Kapoor, vice president of marketing for SoC realization at Cadence; Naveed Sherwani, CEO of Open-Silicon; John Heinlein, vice president of marketing at ARM; and Jeff Lukanc, director of engineering at IDT. What follows are excerpts of that conversation, which was held in front of a live audience at the Global Technology Conference in Santa Clara, Calif.

LPE: What is the definition of a mainstream process node these days and why are older nodes so important?
Heinlein: We’re thinking of mainstream as 55nm and older. That’s where a lot of the high volume is. Even though it’s sexy to talk about the leading edge, last year about 75% of ARM’s royalties came from cores that were developed in 2006 and earlier. About 3 million of the 6 million cores we shipped were ARM 7.
Ng: From a manufacturing standpoint, the volumes are at 65nm. From that node it’s moving from 55nm and 40nm, but that’s still the bulk of the industry. A lot of companies are doing some very cool things that are very relevant today at those nodes. Even with some of the biggest companies, a lot of the volume is at 65nm. It’s what pays the bills. If you have 200mm capacity, those fabs are completely depreciated.

LPE: How about for the tools? Does the mainstream part of the market really pay the bills?
Kapoor: From an EDA perspective, 65nm pays the bills as much as 28nm and 20nm.

LPE: Is everything still following Moore’s Law? If a company is designing at 65nm, does it necessarily move to the next node?
Sherwani: We look at everything from networking to consumer applications. Some customers need the latest technology. But there are others who are at 0.18 (microns) and thinking about 0.13, and maybe they don’t to go there. The velocity of that move is segment-specific.
Lukanc: The mainstream for production is 0.13, but a lot of the new designs are ramping to 65nm. We’re looking at older technology and combining new things through integration. There may be a call management IC with a 30-volt option at 0.13 or 0.18, which allows the unique combination of analog and digital management on one chip. We can re-use some of the older technologies.

LPE: There’s a lot of investment in older processes these days. Why?
Sherwani: I visited about 10 fabs in China and I was surprised that none of them had 65nm processes. Most didn’t even have 90nm processes.
Ng: If you look at what’s driving a lot of technology today, it’s the consumer market. And that’s very cost-conscious. If you can’t take advantage of the latest technology, then you look at where your given application makes sense. Cost is very much a factor that customers consider at each process node. And for us, we have to find ways to keep investments in fabs relevant to our customers. We have a big focus on high voltage and power management. We have to find ways to add value on top of baseline logic, which is a commodity at this point.
Heinlein: If you look at smart phones, everyone is always focused on the processor and the high-end chip. But alongside those are the power management controllers and display drivers and RF/mixed signal. Another area for derivative value-added processes that Walter (Ng) mentioned is low leakage. When you get to 65nm leakage is a problem. There are ultra-low leakage variants and high-voltage variants coming out at the high end and the low end, so people can put those into applications that can run on a coin-cell battery for 10 years. To complement that there are ultra-dense libraries that bring the cost and the leakage down and which are suited very well to these kinds of applications.

LPE: If you develop a chip at 180nm and the process changes to low leakage or low power, does it yield the same?
Ng: The strategy in developing these new processes or modules on top of derivatives is to preserve the investment that was made earlier. It takes advantage of the proven solutions that are already there. When we originally developed those processes, at that time they were leading-edge processes. As you get much more volume using those processes, the manufacturing window becomes quite tight. You could probably tighten up the bit cells. But it’s a business tradeoff whether you re-invest in that or not. The yields are just as good.

LPE: What happens to the tools and the IP that was developed?
Heinlein: For the most part it all works. If you think about 180nm, nobody cared about leakage because it wasn’t an issue. Now, when people look at 180nm, they do care about leakage and power management. So we’re putting that back into 180nm.
Kapoor: The innovation at the leading nodes is going to drive benefits at the older nodes. You drive it back in terms of products, but you also drive it back in terms of design techniques. We developed a 28nm PHY, and we were challenged to do it differently because it’s for a leading node. Today we’re applying what we’ve learned back to 40nm and 65nm.
Lukanc: The best tools are developed at the leading nodes, but you may want to characterize older libraries for low power and power management.

LPE: If you improve an existing technology at an older node, can you charge more for it?
Lukanc: Yes. In general, what we’re offering is value-added solutions. In some cases we offer value-added solutions that are low power.

LPE: Will it be essential for older processes to be updated when we get into stacked die as a way of decreasing the overall power budgets and physical effects?
Sherwani: The answer is different for each area. There is no single, simple answer to that.
Kapoor: For a long time our industry has looked at the technology piece rather than the economics. The answer is, it depends. Can you get more value out of an older node? Yes. The economics will drive the longevity of nodes and what you can get out of them. But we cannot talk about the value of older nodes unless we invest in the newer ones.
Lukanc: If you have an existing product, you can look at the option of integrating oscillators or an EEPROM or something else on top of it to reduce the system cost. There are lot of things you can do in a package to reduce the overall cost, but you have to look at the total system cost. You may be offering a smaller footprint to the customer, but they may not be getting value out of that.
Heinlein: If you look at mixed signal and RF design at the leading-edge nodes, it’s really tough to get the transistor variation to be complementary to the analog. There’s a point at which it’s too hard, and in that case a heterogeneous 3D package makes sense.
Kapoor: With 3D ICs there’s a technical capability about whether you can marry different die. But you also have to look at it from a system capability. When you look at tablets, where the SoCs are talking in very high bandwidth to memory, that makes sense. The technology by itself won’t be an answer. You need to find out where it makes sense to use it.

LPE: Is investment in older process nodes an arms race that favors the big foundries?
Sherwani: The specialty foundries being built in places like China have nothing to do with companies like GlobalFoundries and TSMC. They will ship a lot of silicon. Over the next 10 years a lot of the analog silicon will be shipping out of China using all older nodes.
Kapoor: Those boutique fabs are certainly making investments in areas in which they specialize.
Ng: You have to continue to make fabs relevant and to drive a good margin. A big impetus for us in developing modules on top of our processes is that you do get the second- and third-tier foundries coming in and taking the floor out of the base logic price. That’s difficult for us to compete with. So we’re looking at where to add value and how to win a good percentage of market share. We have our investments in 200mm. We will continue to invest there.
Heinlein: We definitely see lots of specialty processes at the smaller players. We work with them and enable them. But once it gets to a certain point in the market they we work with the big players.

LPE: Will it become a battle of who has the deepest pockets?
Sherwani: The good thing about older nodes is that the investment needed is miniscule compared with the tens of billions of dollars at advanced nodes. A lot more players can be relevant at older nodes. At 14nm I don’t think there will be more than three or four players.
Ng: The incremental investment to bring up these value-added modules is nothing compared to the investment at the leading edge. The other side is that the equipment manufacturers are a leading component of the cost at the leading edge. At the mature nodes, you’re not buying a lot of new, expensive tooling.
Lukanc: That happens on the product development side, as well. To do a 100 million-gate design requires a certain amount of tools and people and mask costs. At the older technologies mask costs are quite cheap. And if you’re re-using technology and adding to it, you can keep NRE low so return on investment is quite high. You need to take advantage of mainstream older nodes as well as more aggressive nodes.
Ng: And most times our relationship with most of the leading-edge companies span multiple nodes.
Kapoor: At 14nm there are 5 or 10 customers. As a foundry, you have to worry about how you’re going to get the rest of the industry in. The economics even for the companies that can afford it aren’t that great. So you’re going to see continued innovation even at the older nodes.
Ng: A major part of the foundries’ concern is up and down the supply chain. It’s not just the fabs. It’s the tools, the support for IP providers, and packaging solutions. That’s a challenge we have to address as an industry.