By David Lammers
Analog and mixed signal (MS) devices will play an ever-increasing role in saving energy, particularly as the “Internet of Things” expands to about 10 billion units per year over the next decade. But as leading-edge design rules scale to 28nm and below, enhanced with high-k/metal gate technologies, it is becoming increasingly challenging to integrate AMS devices on SoCs.

Tyson Tuttle, chief operating officer at Silicon Laboratories, said demand for mixed-signal technology will accelerate in an energy-conscious world. As people turn to electric vehicles, solar energy, and the “Internet of Things,” mixed-signal sales will increase sharply. “People will pay money to save energy,” Tuttle said at a Global Semiconductor Association (GSA) event held in Austin, Texas. For example, the embedded devices that rely on harvested energy, such as electricity harvested from vibrations, will become a multi-billion-dollar opportunity over the next decade, Tuttle said.

Increasingly, the “digital-centric” approach to AMS functionality is being employed to improve power consumption. AMS “enables new ways of managing energy and resources,” he said, citing smart meters, which deliver real-time monitoring of power consumption as one example.

Mixed-signal devices are about one-tenth of the $300 billion chip industry now.

Silicon Labs has shipped about a billion radio chips, which provide the FM radio function on handsets, personal media players, and other systems. The company is gaining traction in the integrated CMOS TV tuner market, which Tuttle said “is a hard problem” due to multiple broadcasting standards, noise margins, and other challenges.

While the topic of the event was the confluence of AMS and 28nm technology, few are close to the leading edge for largely AMS products. Silicon Labs uses relatively relaxed design rules (55nm at 2.5V is the most advanced process, and 90nm is common for chips with embedded flash). Tuttle said “it will be a while” before the TV tuner chip goes to 45nm technology, for example, partly because of mask costs. “There is no one application or chip right now that will pay for a 28nm mask set.”

While digital and analog use much different process technologies, digitally-assisted mixed signal hews closer to the leading edge. (Source: Silicon Laboratories)

AMS technology is becoming more challenging at 28nm. At the GSA event, only a few hands went up when the panel moderator—Mahesh Tirupattur, executive vice president of Analog Bits—asked how many people in the audience were designing at 28nm design rules. Jose Alvarez, design collateral manager at Freescale Semiconductor, said his company has several 28nm SoC designs underway.

“There is a significant amount of analog work, a lot more than we originally thought,” Alvarez said during the panel discussion on the challenges of 28nm AMS technology. As SoCs move to fast Serial I/O buses, design teams are being challenged. Clocking of the dozen or more phase locked loops (PLLs) is “very complex,” he said. Packaging is another challenge, he said, noting that 3D stacked ICs may be used to incorporate “high-end analog into low-end SoCs.”

3D and 2.5D (interposer) integration will provide “a boon for MS integration if the thermal issues can be worked out. I think we’ll see a lot more 3D packaging at 28nm and below,” he said.

“Today’s complex SoCs are throttled by power considerations,” Alvarez said. Putting circuits to sleep is one solution, but the design challenge is “putting the hooks in there to make sure those circuits come back to life” in a timely fashion.

Ana Hunter, in charge of Samsung’s U.S. foundry operations, said Samsung has several 28nm SoCs in the prototyping phase now, with 20nm devices headed toward shuttles, all including extensive AMS technology.

The panelists agreed that HK/MG and double patterning provide additional challenges. While HK/MG technology will reduce gate leakage, the metal gates result in increased variability, requiring more stringent circuit simulations. Similarly, double patterning introduces adjacent metals, oftentimes on different masks, which requires improved static timing analysis to ensure that the timing circuits work correctly. Extra margins and restricted layouts may be required.

The result is increased spending on AMS IP. Sanjay Krishnan, a management consultant at Keystone Strategy Inc., said about 40 percent of the intellectual property (IP) owned by foundries is analog mixed signal (AMS), while only 30 percent is digital IP. Foundries such as TSMC and Global Foundries are building up their AMS IP libraries in order to “add value like Apple did, creating their own ecosystems.”

“As AMS moves to the foundries, IP becomes more important,” Krishnan said. “The industry is evolving, going to more external IP. It is all part of the disassociation of the supply chain,” he said.

By Ed Sperling
The number of factors required for an effective power model has far surpassed the capabilities of even the most detailed spreadsheet at 45nm and beyond. It has now entered the realm of complex databases and architectural tradeoffs, and those tradeoffs will become even more complex as 3D stacking takes root over the next 24 months.

The idea of modeling power is hardly new, but you wouldn’t know that comparing the current iterations side-by-side with the old methods. While there is still a need to understand worst-case scenarios to protect signal integrity, not to mention the other components on a chip, there is far more that needs to be considered in power modeling at advanced nodes than in the past.

“There are two issues that need to be solved,” said Ran Avinun, marketing group director for system design and verification at Cadence. “One is how to do this. The second is who owns the format. The methodology hasn’t been solved yet. When you tell the customer that we’ll compare our numbers with your back-end flow and libraries, that’s not good enough. It’s going to give me the data about the SoC or the ASIC, but that’s not enough. When customers look at power it’s what they measure in the lab. When they test the device it’s in a real environment with real software and the package. Today they don’t have a good way to test. It’s done with software and vectors, but it’s not really reflecting what the user will get.”

The second issue is understanding what parts of the system actually consume power. “Customers don’t know how to partition the power consumption of the ASIC vs. the overall system, so what they measure is the overall power. They don’t know how to partition those components and there is no good way to model that. We’re looking at the ASIC and die level, but they need to model the whole system,” Avinun said.

Moreover, for the system-level numbers to be used in a meaningful way at the architectural level they have to be relatively accurate. The shrinkage of components has made everything more susceptible to the effects of power, mechanical and thermal stress, electromagnetic interference, electromigration and noise (see fig. 1). Modeling power is now required. But even the simplest ideas such as power supplies are no longer simple.

Fig. 1. Source: Apache Design Solutions

“In the past we had two power supplies, one for the digital and one for the analog,” said Cornelia Golovanov, an EMI expert at LSI. “Now we have three or four analog power supplies in a small area, which makes the supplies very inductive. These are not well analyzed in the context of the whole system.”

Like anything else at advanced nodes, without adequate planning power supplies can be corrupted. Even maximum power, which used to be calculated in a worst-case scenario fashion once RTL was already synthesized, has become incredibly complex with multiple power islands, multiple modes, multiple cores and multiple voltages.

“With a power model ideally you want to cover all scenarios and all vectors,” Golovanov said. “But some of these have really long simulation points. It can take weeks at the end of the design cycle, and then you have to factor in the chip in the package on the PCB. There is no time for that.”

What’s in the model?
That’s where models fit in. Much attention has been paid to the different library approaches for defining power intent with the Unified Power Format (UPF) and the Common Power Format (CPF). The power model is a level above that, defining the power delivery network, signal integrity analysis, electromagnetic interference and compatibility (EMI/EMC) and the thermal effects of power, primarily in the form of dynamic and static leakage.

“In the past power models were simplistic in nature and deemed sufficient for the needs at that time,” said Aveek Sarkar, vice president of product engineering and support at Apache Design Solutions. “You could provide a single current and single capacitance and the result was your best guesswork. That all began to change in 2006 when we moved to 65nm. The package design could no longer be off the shelf. It’s now a competitive difference for companies and it can determine the price and performance of a system. Hence, an accurate model that represents the actual activity and parasitic profile of the chip is important off which you can base package and PCB decisions.”

Packaging has other issues, though. While a chip consumes current, the package and the PCB can act as an antenna for chip-generated noise, which results in EMI. It’s becoming necessary to extract an S-parameter model (scattered parameter) model for the package. Once that model is constructed, then a full system-level AC, DC, and time-domain analysis, then a full analysis can proceed using the power models of the chip, said Sarkar.

“Right now 40nm is mainstream,” he said. “At 22nm and 28nm electromigration gets very complicated. Since electromigration and leakage current can change very drastically with a temperature increase, we have to model the thermal profile of the chip–especially for a stacked die configuration.”

But there’s also a point where models can become useless. Looking at everything from a very high abstraction level is excellent for layout and functionality, but it can insert some very large errors into power models—sometimes as high as 300%, according to Cadence’s Avinun.

And there needs to be more consistency among models to make them useful. Frank Schirrmeister, director of product marketing for system level solutions at Synopsys, said the standards don’t yet exist because this is all so new.

“In TSMC’s reference flow 11, they characterize their libraries for low power and then make this all accessible for TLM 2.0 modeling,” Schirrmeister said. “Then you should be able to add up meaningful power numbers, even at the system level. Today this is all in the early stages. The different vendors have different formats. At some point it needs standardization.”

Standards needed
All of the major foundries are working on these kinds of models. In addition, Apache is working with the GSA on models for power. Those will become particularly useful in stacked die configurations, where thermal issues are not always intuitive. (See fig. 2)

Fig. 2. Source: Apache Design Solutions

None of this will get solved quickly. For one thing, power models generated by memory makers may be different than those generated by foundries and IP vendors, which is where standards will become important. But the first step is creating a dialog and generating tools that can provide visibility inside and SoC, and so far at least that seems to be happening.