By Pallab Chatterjee
FinFETs, stacked die, heterogeneous interposers, TSVs, 450mm wafers, new interconnects and everything with MEMs and sensors is what the last few weeks have brought. A number of major announcements, technology releases, conference updates have identified these technologies as the future of IC design.
At ISQED, Robert Geer, chief academic officer at the College of Nanoscale Science and Engineering in Albany, N.Y., discussed nanotechnology programs while highlighting the construction of a new building dedicated to 450mm wafer fab development. This new fab will support R&D for equipment, devices, and processes for the wafers that just a few years ago fell under the heading of, “most likely not going to happen.” The facility will work on lithography, front end of line (FEOL) and back end of line (BEOL), as well as adjustments to and planning for the logistics for managing these massive and very heavy wafers. This is being done concurrently with further development into the single-digit nanometer process and device technologies. These new flows and processes target devices with operating voltages of less than 0.8v, breaking the 1 volt threshold that has been dominant for more than 50 years.
Adding into to how these new processes will perform, the Common Platform Group (GlobalFoundries, IBM and Samsung) presented 20nm high-k/metal gate flows and identified this is the end of the line for Planar CMOS. Beyond 20nm, the next-generation devices will be FinFETs, with more exotic devices to follow below 10nm. Better control of leakage, as well as improved low-power performance, are due in part to these new devices not having a diffused source/drain in the bulk or epi material, which can serious impact secondary current paths. However, the devices do raise several new concerns, not the smallest of which is the device description. Instead of just W and L, designers now will have to add Z. This impacts simulators, netlists, and physical build/verification of the designs.
While most of the talk has been on process capability, there also is a lot of attention being focused on changes in IP and design methodologies. A consistent theme in these discussions is that power is the No. 1 design constraint and drives even functionality for the definition of new designs. Power, and the new soft metric of performance per watt, are the basis for these new $100M design development projects. IBM and Samsung executives noted that the economics of these new designs have changed significantly.
The basis of power as the overall constraint has now brought the impact of packaging and other modules into the design process. Local thermal balance, power distribution, bonding methods, stacked die, and signal interconnect to adjacent devices are now required parts of the initial SoC design.
MEMS is a case in point. The key issue MEMS developers wrestle with are power and accuracy, rather than speed. Most of the MEMS systems have 16-to-30-bit accuracy on the sensor element, but the challenge is getting these signals to the data-processing electronics with as little disruption using as little power as possible. Noisy interfaces consume power and reduce the signal integrity and accuracy of the main datapath. As the Internet of Things progresses to have sensors in everything, the power shifts from the logic processing section to the RF and communication circuitry. These blocks have to be balanced with the reporting rate, which operates the radios, and when the low power data is being collected. The majority of the systems on the Internet of Things are multi-die devices.
TSMC joined the fray with its new interposer announcement. It was not clear by industry naming convention (2.5D, 2.75D, or 3D) what the technique should be called, but it brought major technical advances toward the stacked memory on logic design methodology and the major performance/watt improvement over other technologies. This once again, brings power as the driver to the forefront.