By Pallab Chatterjee
FinFETs, stacked die, heterogeneous interposers, TSVs, 450mm wafers, new interconnects and everything with MEMs and sensors is what the last few weeks have brought. A number of major announcements, technology releases, conference updates have identified these technologies as the future of IC design.

At ISQED, Robert Geer, chief academic officer at the College of Nanoscale Science and Engineering in Albany, N.Y., discussed nanotechnology programs while highlighting the construction of a new building dedicated to 450mm wafer fab development. This new fab will support R&D for equipment, devices, and processes for the wafers that just a few years ago fell under the heading of, “most likely not going to happen.” The facility will work on lithography, front end of line (FEOL) and back end of line (BEOL), as well as adjustments to and planning for the logistics for managing these massive and very heavy wafers. This is being done concurrently with further development into the single-digit nanometer process and device technologies. These new flows and processes target devices with operating voltages of less than 0.8v, breaking the 1 volt threshold that has been dominant for more than 50 years.

Adding into to how these new processes will perform, the Common Platform Group (GlobalFoundries, IBM and Samsung) presented 20nm high-k/metal gate flows and identified this is the end of the line for Planar CMOS. Beyond 20nm, the next-generation devices will be FinFETs, with more exotic devices to follow below 10nm. Better control of leakage, as well as improved low-power performance, are due in part to these new devices not having a diffused source/drain in the bulk or epi material, which can serious impact secondary current paths. However, the devices do raise several new concerns, not the smallest of which is the device description. Instead of just W and L, designers now will have to add Z. This impacts simulators, netlists, and physical build/verification of the designs.

While most of the talk has been on process capability, there also is a lot of attention being focused on changes in IP and design methodologies. A consistent theme in these discussions is that power is the No. 1 design constraint and drives even functionality for the definition of new designs. Power, and the new soft metric of performance per watt, are the basis for these new $100M design development projects. IBM and Samsung executives noted that the economics of these new designs have changed significantly.

The basis of power as the overall constraint has now brought the impact of packaging and other modules into the design process. Local thermal balance, power distribution, bonding methods, stacked die, and signal interconnect to adjacent devices are now required parts of the initial SoC design.

MEMS is a case in point. The key issue MEMS developers wrestle with are power and accuracy, rather than speed. Most of the MEMS systems have 16-to-30-bit accuracy on the sensor element, but the challenge is getting these signals to the data-processing electronics with as little disruption using as little power as possible. Noisy interfaces consume power and reduce the signal integrity and accuracy of the main datapath. As the Internet of Things progresses to have sensors in everything, the power shifts from the logic processing section to the RF and communication circuitry. These blocks have to be balanced with the reporting rate, which operates the radios, and when the low power data is being collected. The majority of the systems on the Internet of Things are multi-die devices.

TSMC joined the fray with its new interposer announcement. It was not clear by industry naming convention (2.5D, 2.75D, or 3D) what the technique should be called, but it brought major technical advances toward the stacked memory on logic design methodology and the major performance/watt improvement over other technologies. This once again, brings power as the driver to the forefront.

Data Center Strategies
One of the most lucrative markets for processors is at the data center level. While improving efficiency in mobile devices is a competitive advantage because it affects time between battery charges, inside the data center it is measured in dollars. It costs some companies millions of dollars each year to power servers and to cool them.

That accounts for the rush to add virtualization into data centers, and the rising fortunes of both VMware and Citrix. It also feeds into the private cloud fortunes of companies such as IBM, and the massive reorganization underway inside of Hewlett-Packard. But at the bottom of the stack, powering all of this, there still has to be a processor. And it is the density of processors, coupled with inefficient use of them, which has caused this scramble inside corporate data centers for a way to cut costs.

Water cooling has returned as one way of dealing with excess heat—IBM re-introduced plumbing a couple years ago. A second approach has been to raise the temperature ratings for servers, which Dell instituted last year. But a third approach has been to reduce the overall amount of heat being generated in the first place by adding more efficiency into the data center on a macro scale.

AMD’s acquisition of SeaMicro gives a hint of what’s to come. SeaMicro has created a supercompute-fabric technology—the basis of a mesh network that can pull resources as needed. Virtualization companies such as VMware are heading in this direction, as well, with data-center load balancing. But a mesh network takes that approach one step further, dynamically adding more resources when necessary. This is the goal of cloud computing, and these are the latest pieces to make it work.

So can more energy be saved with that approach than trying to improve the individual pieces. The reality is that everything helps, and everything saves money. But it will take time to sort out exactly how much efficiency is gained by each part, and which investment will pay the biggest dividends. For more information, Mentor Graphics’ Barry Pangrle has taken a deep look at this subject.

For now, the good news is that work is underway to improve efficiency on all fronts. But don’t be surprised when the numbers start rolling in to find a series of rapid acquisitions as companies look to strengthen their competitiveness through combinations of more efficient technology.

Hidden Costs In Advertising
Most people are annoyed when they get cold-called for marketing their cell phones because they’re paying by the minute. But what is less obvious is the amount of power being consumed by the advertisements in free mobile applications. A team of researchers at Purdue and Microsoft found that up to 75% of the energy consumed by the applications is caused by ads.

Of particular interest is the number of “wakelock” and “energy” bugs. Just as there’s no free lunch, there’s no such thing as a free app—unless, of course, it’s open-source and monitored by an independent group with high-minded aspirations. The free apps available for smart phones generally don’t fall into that camp.

A white paper on the subject was published by Microsoft and details the energy consumption of popular games such as Angry Birds, Free Chess, as well as popular information sites such as the New York Times and MapQuest.

This is interesting research, partly because it shows how to detect software power issues, and partly because it shows how users can affect their own battery life even using the best-designed systems.

–Ed Sperling

By Mark LaPedus
For some time, DRAM makers have been developing 3D memory chips, but commercial products still are not due out for some time because of technical and cost issues.

But the advent of the 3D DRAM era could be near the turning point, as two memory rivals have separately moved to bring their respective technologies closer to production. In one move, Micron Technology Inc. has disclosed the manufacturing flow for its recently announced Hybrid Memory Cube (HMC) technology, a 3D DRAM scheme geared for high-end servers and networking systems. Under the plan, IBM will manufacture the controller logic portions of the HMC within its own fab. Micron will make the memory portions, as well as assemble and test, the HMC devices within its own operations.

On another and more surprising front, Japanese DRAM maker Elpida Memory apparently has beat its larger rivals to the punch by announcing the industry’s first commercial Wide I/O DRAMs. The first device from Elpida, dubbed Wide IO Mobile RAM, is a 4 Gbit device based on a 30nm process technology and a 3D structure using through-silicon vias (TSVs). Elpida plans to sample its first Wide I/O DRAM devices this month. The devices are geared for next-generation smartphones and tablets.

Samsung Electronics Co. Ltd. and Hynix Semiconductor Inc. are also separately developing 3D DRAMs. The idea behind a 3D device is to stack existing die and connect them using TSVs, thereby lowering the resistivity and boosting the bandwidths. But the problems with 3D devices based on TSVs involve cost, technical issues and supply-chain headaches.

“There is a lot of attention and engineering resources being thrown at 3D right now by all DRAM developers, including Samsung, Micron, Elpida, and Hynix,” said Mike Howard, senior principal analyst for DRAM and memory at IHS iSuppli. “Wide I/O has yet to really reach a cost level that makes it competitive and we are likely still a few years away from mass adoption. Elpida may very well have a functioning part in the lab and may be able to produce test samples, but I think we’re still a few years away from this being used in anything but the most premium markets.”

Hank Lai, product planning for memory marketing at Samsung Semiconductor Inc., said Wide I/O DRAMs are not expected to gain traction until sometime in 2013. At present, smart phones and tablets are using plain-vanilla, low-power DDR3 DRAMs or mobile DRAMs based on the LPDDR2 interface standard. Before Wide I/O, the mobile market will move from LPDDR2 to the next-generation LPDDR3 interface standard, Lai said.
LPDDR2 has a maximum throughput of 8.5 Gbytes/second. LPDDR3 has a peak throughput of 12.8 Gbytes/second. Samsung claims its new LPDDR3 devices consume 20% less power than LPDDR2.

Elpida’s Wide IO Mobile RAM has 512 I/O pins. The device is said to achieve a data transfer rate of 12.8 Gbytes/second, roughly similar to LPDDR3. But Elpida’s Wide IO Mobile RAM has a height of 1.0mm, compared to 1.4mm with existing mobile DRAMs based on today’s package-on-package (PoP) technology.

Elpida acknowledged that the Wide I/O market will take time to evolve. The 4 Gbit Wide I/O DRAM will sample next month, but production “will take place sometime in the second half of 2012,” according to officials from Elpida. “For volume production, it will be sometime in 2013.”

In March of 2012, Elpida plans to sample a 16-Gbit DRAM, which is based on stacking four 4-Gbit Wide IO Mobile RAM chips. Mass production is due sometime after 2013, according to Elpida.

On the other end of the spectrum, Micron and Samsung are moving full speed ahead with HMC. “This is a slightly different product than Elpida’s and is targeted at server customers. The specs are very promising, but again, this is still a few years from hitting the big time—2013 at the soonest,” Howard said. “Samsung is also a part of the HMC group, lending weight to the product’s chances.”

In October, Samsung and Micron announced the creation of a consortium to develop an open interface specification for HMC. Micron is the actual designer of the HMC technology. Micron and Samsung, as well as Open-Silicon, Altera and Xilinx, are the founding members of the Hybrid Memory Cube Consortium (HMCC).

HMC will incorporate DRAM arrays stacked on a logic chip. The device is connected with 2,000 to 3,000 TSVs. HMC prototypes are said to clock in with bandwidth of 128 Gbytes/second.

It is not a widely known fact, but fabless ASIC house Open-Silicon is developing the controller IP for HMC. Colin Baldwin, director of marketing and business development for Open-Silicon, said the HMC controller will be based on the company’s Interlaken controller IP. Interlaken is a high-speed, chip-to-chip interface protocol that builds on the channelization and per-channel flow control features of SPI4.2. The Interlaken controller will serve as the interface between the memory and physical layer to help “boost the bandwidth” in the device, Baldwin said.

On the manufacturing front, the HMC device itself will go through a two-step process. The controller logic portion of HMC will be manufactured at IBM’s semiconductor fab in East Fishkill, N.Y., using the company’s 32nm, high-k metal gate process technology. IBM also will handle the TSV creation process based on Micron’s specifications.

Micron will develop and make the DRAM arrays in-house based on a 3xnm process within its own fabs, said Mike Black, a technology strategist at Micron. Micron will take the logic controller from IBM—and the in-house made memory arrays—and then will assemble and test the entire HMC device within Micron’s R&D production line in Boise, Ida, Black said.

Micron is in the qualification stage with the device. “We are feeling pretty good about it,” he said. “Most of the learning is done.”

By Ed Sperling
Mainframes, despite the bad rap they received in the 1990s era of client/server computing, have always been a trendsetter in computing. Virtualization, multiple cores and parallelism were all outgrowths of more efficient mainframes. So was middleware and the concept of a hypervisor.

The latest change is an energy-efficient supercomputer. In the past, supercomputing and efficiency weren’t terms that were mutually compatible. Supercomputing relied on the most powerful computers available. It was like trying to set the land speed record in a automobile while also worrying about gas mileage.

IBM’s latest iteration is the PowerPC A2 processor, which contains 16 compute cores plus a separate core for operating-system functions and an extra spare core. This is the mainframe version of what IBM originally did in the Cell processor, an eight-core processor of which six were used for gaming and one was used for management.

IBM introduced the A2 in February 2010 at ISSCC. The cores run at 2.3GHz, each with 8MB of cache. It also uses a concept called “regular expression,” which matches strings of text. The idea dates back to the 1950s and basically is a pattern-recognition scheme that speeds results. When paired with large caches and powerful memories, it produces a more intelligent computer such as Blue Gene, which blasted away human opponents in Jeopardy.

What’s particularly different, though, is that all of this runs at 55 watts, which is less than a typical desktop computer, using an SOI substrate and much more efficient software. The extra management core minimizes interrupts by routing them to any available cores, rather than slowing down the main compute process. This is a big step forward in more efficient computing, and it raises some interesting possibilities for the future of operating systems in a multicore world.

At last count, the A2 had 1.47 billion transistors and measured 19mm(2).

By Pallab Chatterjee
Power became the driving discussion at several major events last month.

The global cries for energy reduction, which have been mainstream since the early 1970s on the political level, have now moved to being real economic realities for component and systems suppliers. Chipmakers are finding that lower power makes good economic sense—lower cost of packaging, lower cost of ownership of the products, higher reliability and, most importantly, the differentiation in power reduction methods is resulting in a lower cost of sales for the products as it is increasing the customer retention.

Once a methodology is selected for the chips, it is carried through to the board, then the system and eventually the software that runs on it. This makes the cost of changing the power method very expensive and typically keeps the customer on multiple generations of hardware and components from the same suppliers under the same software umbrella.

The Hot Chips conference featured several dramatic network and multicore server products that all had enhanced power management. The power management formally was multiple rails (I/Os and cores) and sometimes a thermal shutdown. The new systems are pervasive to the point that architectures are created with equal attention paid to power management and data throughput. The features shown were multiple power supplies, variable power voltages, block-based shutdown and turn-on, new circuits to minimize turn-on/turn-off, alternate clock tree distribution systems, lower power PLLs and clocks, and even new logic methods.

Fulcrum presented a 1 billion packet/second frame processor, which ended up being a case study for the applicability of non-synthesized sequential logic or asynchronous design. The logic structure, while known in the past, has never been implemented in such a large-scale application before, and the results included not only better performance but a power envelope that was task-acceptable.

Similarly IBM, Intel, Tilera and Cavium presented next-generation many-core designs with performance targeted at application needs over the next 5 to 10 years, but with power profiles at levels similar to chips of many decades back. The general rule is that power per transistor in these designs is less that 100 times what it was five years ago.

On the system side, data centers are the driver. Dell addressed the issue of power reduction for its servers by not just swapping components, but also re-qualifying the systems to work at extended temperature ranges. This means peak air temperature can be as high as 113 degrees Fahrenheit (45C) for its servers without sacrificing performance or warranty. This increase from 80 degrees Fahrenheit means there is no need to provide chilled air to cool the machines. The cost of the environmental air is generally equal or greater than the cost of the energy to run the servers.

To keep the component power down, these servers use new 30nm DDR3 DRAM from Samsung, which are now down to operating at 1.35V from 1.8V. The reduction in the power supply, and the reduction of geometry to make the devices, provides higher performance, higher density and an overall reduced power envelope. Google has noticed that by using virtualized machines and high DRAM on its servers it can eliminate the power from rotating media and go to mostly high-memory machines. This architecture systematically drops power at the data center level by double digit percentages and provides an increase in performance. The performance increase allows for the implementation of new features such as “instant search” while a user is inputting the full search field.

Facebook, which is new to the game on hardware, took a fresh look at power and started not with the chips, the memory or even the board, but with “how is the power getting to the computers?” It was able to provide a 12% to 15% reduction in power by looking at and redesigning the power supply input (408V to 24v signal path) and eliminating the UPS in its servers. This is a new area of high-power and high-current design that companies need to think about and look at. Facebook also ended up changing the board designs for the base compute server modules. Information on the Facebook approach and other areas to address the power can be found at OpenCompute.

Power as defined by the EDA community, which is “dynamic peak power in active mode,” as well as in idle mode, multi-mode and transition, and even infrastructure, will all play key role in next-generation low-power design.

By Ed Sperling
How do you interface with your electronics? For decades, the only way was a keyboard. Then came the mouse and other pointing devices. Then came voice commands. And finally, we have entered the realm of touchscreens.

In the future, it will probably be all of the above—and more. Kurt Shuler, marketing director at Arteris, in his blog this week pointed to gesture recognition as the next wave in interfaces—basically a way of making interactions even better. IBM had pioneered some lip-reading technology back a decade ago, which leads you to wonder exactly why it took so long.

But the current market for these devices may be less about what can be done than what can be done within a given power budget. Pattern recognition and movement has been part of artificial intelligence for decades. IBM even developed a database that can recognize shapes, and Bell Labs prior to the sale of Lucent was working on a program that could identify parts of faces and shapes of heads, with a distribution of probabilities for correct identification.

Semtech yesterday rolled out a proximity sensing and haptics control that it claims to be ultra low power—2.3 volts to 3.6 volts. For a device with a plug, this is a non-issue. But for mobile devices that are in sleep mode or off most of the time, waking up quickly with a touch or a gesture will be more difficult. Interfaces require at least something to remain on, and with power budgets being what they are, and more functionality on chips, it remains to be seen just what gets implemented on mobile devices.

By Ed Sperling and Pallab Chatterjee
As software teams continue to race past hardware teams in numbers of engineers, hours spent on designs and NRE budgets, companies are beginning to question whether there needs to be a fundamental shift in priorities and strategy.

The problem is that it takes far too long to write and debug the software and to get it working on the hardware, even with virtual prototyping capabilities.

“Bare metal software is the hard part of the problem,” said John Bruggeman, Cadence’s chief marketing officer. “It’s the bane of the embedded system company—80% of the time is spent getting bare metal software to run on hardware. It takes two to three months to get Linux to boot because there is no visibility into the software and the hardware simultaneously.”

That challenge becomes increasingly more difficult at each new process node, as well, because complexity is increasing on both sides. Bruggeman said there are three reasons solutions haven’t worked so far. One is that every solution to date has been closed or proprietary, which limits the number of programmers working on a solution. The second is that solutions today are fragmented, both by multiple vendor tools as well as some of the flows by single vendors. And third, the complex multi-geographic development coupled with enormous scale and size has not resulted in a coherent solution.

Cadence clearly isn’t alone in recognizing the growing problem in software, although it is the most vocal of the Big Three EDA vendors. All have major software efforts under way and have made significant investments in these areas. Mentor Graphics has a big push in Embedded Software and Synopsys has an equivalent focus on software prototyping. All have made acquisitions in their respective areas, as well.

But getting software to run more efficiently on the hardware is a different sort of problem. It’s understanding how the two interact at a very deep level.

Glenn Perry, general manager of Mentor’s Embedded Systems Division, recounts a story of one customer that was porting Linux to a chip and couldn’t figure out why the operating system was continually burning up energy. The culprit, as it turned out, was a blinking cursor.

“The goal is to put power in front of software,” said Perry. “When we do that with a regular optimization of Linux we see a 70% to 90% improvement in power. We need to fix the simple stuff first, and this isn’t so easy. What we’ve found is that embedded developers know very little about software.”

Power games
But if hardware engineers know little about software, the reverse is also true. One of the biggest demands for improving the efficiency of software comes from the gaming world, where software typically has been written in a high-level language with little or no attention to power consumption. In gaming, the user focus always has been on performance—both in speed and in resolution—rather than power. But as more games are being downloaded onto mobile devices, that perception has changed dramatically. No matter how good the game, if it drains the battery in 20 minutes no one will buy it.

The result is that power controls need to be specified in the code, which is difficult considering the growing demands on these systems. Most online gaming is done at 720p resolution due to bandwidth limitations, with a typical compression of 1 I frame for every 200 P frames as part of the H.264 codec.

Mobile platforms typically code in OpenGL while 3D games use OpenCL. These games use a shader, 3D render, and main graphics display engine for the iPhone, iPad, Samsung phones and tablets, LG phones, Motorola and Droid phones, Asus tablets and the Motorola Xoom. Several mobile gaming companies (France, Itally, Finland, Sweden) are now developing products for Q4 release using OpenCL for the Imagination Technology PowerVR core.

The challenges are growing from there, as well. Several major software companies, to provide a higher quality visual experience, also have written a new codec for use with the Xbox360 and PS3 platforms. These new codecs handle a different raster and render routine that supports both physics-based graphics generation (fire, rain, water, snow, wind, explosions, and striking reactions from swords/sticks/knives) and secondary scan for background details (flowers on trees, multi-color grass, flowers and moss on the ground, details on reeds, etc.) in addition to the normal patterns. The new codec was needed to be able to send and render the data in the standard data stream size.

Which comes first
So how much is all of this really going to affect design? Despite predictions that software engineering teams would displace hardware teams, the reality is that both will be forced to co-exist. They will never actually speak the same language or work on the same exact project, but the push is to improve communication back and forth between them. Software needs to become far more power-aware, and hardware needs to become more efficient at running software.

The last time the design world dealt with an issue like this was when the battle over RISC vs. CISC—reduced instruction set computing vs. complex instruction set computing—was being waged. That was in the 1990s, when Unix first posed a commercial challenge to operating systems from companies such as IBM, Hewlett-Packard, Digital Equipment Corp. and a handful of others that made their own OSes back then.

But power is forcing these issues back on the table once again, driven initially by the mobile sector and increasingly by devices with a plug. The likelihood is that it will never be a perfect marriage, but it is one that is likely to last this time because both teams need to at least have the same goal—even if they don’t talk the same language.

By Ed Sperling

The Other 3D
Intel will roll out processors using tri-gate finFET transistors at 22nm, which it says will sharply lower the operating voltage, boost performance and reduce leakage.

Multigate transistors have been the subject of research for decades, most prominently at UC Berkeley, because they can be used to reduce current leakage and increase density. Going vertical allows more transistors to be loaded onto a piece of silicon, which in the case of a processor is particularly important because more transistors can translate into better performance.

Intel claims the new structures will improve performance by 37% at low voltages. The company said that makes it ideal for small handheld devices, a market where Intel has not done very well in the past primarily because its chips are considered power hogs next to those using ARM and MIPS cores. That statement alone caused ARM’s stock to plunge 7% as speculation mounted that Intel could replace ARM cores inside of some Apple devices. This is pure speculation, of course. Apple never talks about that stuff and Intel hasn’t even intimated that. ARM’s stock recovered rather quickly, too.

Still, most companies have shied away from finFETs because they are extremely difficult to manufacture and potentially can add to the design and manufacturing cost. Intel’s big advantage in this regard is that it still owns its own fabs and develops its own manufacturing process, something that is far too costly for all but a handful of chipmakers.

An alternative to 3D structures is ultra-thin body silicon on insulator, which is now being tested by IBM, STMicroelectronics, Soitec and Globalfoundries. And there is a possibility of mixing things up to include both. But the writing is on the wall—big changes are ahead, and Intel’s move is a first big step in that direction.

TI Pushes FRAM
Microcontrollers have been used for years to reduce power in devices through such developments as multispeed motor control and intelligent sensors, but the real battle of late has been inside the microcontrollers themselves. Companies in this sector have been playing leapfrog with power numbers taking priority over performance increases.

TI’s latest rollout includes an ultra-low-power FRAM, or ferroelectric RAM (previously written as FeRAM). This type of RAM uses 250 times less power than EEPROM-based microcontrollers, according to TI, and can be written at speeds of 100 times faster. FRAM is not a new technology. It was developed in the 1990s by Ramtron, and has been manufactured by Fujitsu for more than a decade.

Apparently major strides have been made in the pricing of this technology since then. TI’s microcontroller is priced at $1.20.

By David Lammers
A group of companies within the SOI Consortium, including ARM, GlobalFoundries, IBM, STMicroelectronics, Soitec, and CEA-Leti—said they have created 20nm Ultra Thin Body Silicon on Insulator (UTB-SOI) test circuits that meet the needs of the smart phone and mobile systems markets.

Silicon was fabricated at IBM’s Albany Research Center, using SOI wafers from Soitec with thin silicon and buried oxide (BOX) layers. An ARM Cortex processor, with memory, was fabricated as the prototyping vehicle, with reliable operation down to 0.7V, said Horacio Mendez, executive director of the SOI Consortium. The consortium said performance was roughly double the levels possible with bulk planar transistors.

The test circuits were based on planar, fully depleted transistors, built on SOI wafers with a top silicon layer of about 10 nm and a BOX layer of about 20 nm, Mendez said. In the past, SOI has been limited to high-performance systems. Mendez said the cost of an UTB-SOI substrate has declined quickly. Besides Soitec, SEH and MEMC are beginning to ship SOI wafers with the ultra-thin layers, which assures semiconductor manufacturers of a stable supply.

Also, IBM and its research partners have developed transistors targeted to the low-power market, he said. Partially depleted SOI has been targeted for high-performance markets, with transistors that were necessarily more leaky that their low-power bulk cousins. “This does not mean that low leakage transistors are not able to be fabricated in the technology; they can be,” Mendez said.
In addition, a back gated FD-SOI device can adjust the back gate bias to reduce leakage even further, adding yet another lever to control static power, he said.

Details of the test silicon will be discussed next week at the Mobile World Congress in Barcelona.

By Ed Sperling
Microsoft is looking for 16-core servers for future data centers using Intel’s Atom and AMD’s upcoming Bobcat processor lines in order to lower power consumption in data centers. The announcement, made at the Linley Data Center Conference in San Jose this week poses an interesting dilemma for Intel and AMD—as well as challenges for ARM and even Microsoft.

On the Intel and AMD front, the big question is how such a shift would impact revenues, given the fact that both companies have used the power-saving lite versions of their processors in much lower-cost devices such as netbooks. While some data centers are experimenting with Atom-based arrays for servers, the real savings have come from virtualization to improve server utilization, and cloud-based strategies to quickly ramp up and ramp down compute capacity as needed.

Virtualization has been extremely successful. Most large companies have adopted it to some extent because it costs money to power and to cool a server, whether it’s utilized at an optimal 60% to 85% or whether it’s running at 5% to 15% utilization, which was the industry average prior to virtualization. The problem for Microsoft was that the virtualization was done using VMware and Citrix software, not Microsoft software.

Without virtualization, it’s not entirely certain whether many applications will be able to natively take advantage of 16 cores, considering most currently don’t use more than one or two. In fact, the main applications that can be effectively parallelized are databases, graphically-oriented applications such as Adobe Photoshop, and highly computational scientific applications, where the biggest threat to Microsoft and Intel is Nvidia.

Microsoft’s approach will likely be a more effective management of virtualized applications across those cores so that cores can be turned on and off as needed, but it’s certainly not the only company that sees that opportunity. Virtualization currently uses all the cores indiscriminately, but much more intelligence is being added into the virtualization and middleware layer to cut energy consumption.

For ARM, that means even greater engagement with both Intel and AMD, where it will have to push lower power while defending its performance and the competitiveness of Linux. Given ARM’s grassroots type of ecosystem marketing, it remains to be seen whether it can rise up to the din of the marketing machines of its new competitors. Lower power consumption is a good story, but in the enterprise so are performance and deep relationships.

The old adage that no one ever got fired for buying IBM can now be applied to Microsoft, Intel, AMD and to a lesser extent VIA. Most IT departments have no history with ARM, except in handheld devices, and IT is one of the most conservative purchasing groups on the planet because the stakes of making a bad decision can be monumental. Breaking into the mobile market takes months. Breaking into the IT world can take years, and sometimes even decades. This isn’t a battle fought on technological merits. It’s like a medieval siege. And while ARM may meet the technology challenge, it remains to be seen whether it can meet the long-term marketing challenge.

In this part of the market, the adage about IBM is still true. IBM’s mainframe sales are up, in part because mainframes are still the most secure and effective virtualization environment. IBM invented virtualization in the 1960s, incidentally. And on its newest machines it’s offering water cooling once—which can further cut power consumption because it costs less to cool.