By Ann Steffora Mutschler
The increasing amount of mixed-signal content being included in SoCs for automotive, networking and all manner of mobile devices is reinvigorating the mixed-signal industry. While this is great news for companies playing in anything related to mixed-signal technology, it also means increasing complexity for the engineering teams pulling all the pieces together.

“People have been designing mixed-signal for a long time and the composition of mixed-signal is changing drastically,” explained Mladen Nizic, engineering director at Cadence Design Systems. “Traditionally, mixed-signal was viewed as big digital with some analog in there, but now we see that mixed-signal has really expanded in complexity. So we have designs today that are about equal mixed with respect to analog and digital content. With designs that in the past were predominantly digital, engineers didn’t need to worry about analog impacts and effects. Now they have to, at least to some extent. Digital designers doing verification need to have some representation for these analog parts or mixed-signal parts or they might not completely verify their designs.”

Given that consumers are the driving force behind semiconductor demand today, there are very high performance and cost demands. In fact, cost is now viewed as a primary design variable, according to Navraj Nandra, senior director of marketing for DesignWare analog and mixed signal IP at Synopsys.

Packaging—a significant portion of system cost—plays a deterministic role in the architecture of SoCs because the choice of package dictates a number of technological aspects of the system.

“Our customers are selling package-tested parts, so packaging becomes an important part of the cost equation. Customers would like to use the cheapest possible package that they can get away with, and the design challenge is that the cheapest package has the worst performance in terms of parasitics. You’ve got really bad parasitic inductance, parasitic capacitance, lead frames are very badly put together, and there’s a lot of leakage through the substrates. These things are typically in some kind of cheap BGA or wirebond implementation,” he explained.

To illustrate, Nandra shared a recent situation with a customer that wanted very high performance capabilities on the die but were going to put it into a really cheap package because it was going into a low-end smartphone they wanted to sell under $200. “The discussion was around how to get a very-high-speed memory to connect to the chip being developed without compromising signal integrity. In that particular package configuration that they had, there would be a limitation on speed. At a certain speed they’re going to get skew and reflections on the line, which is going to impact performance of the chip. Then the customer asked if they could save cost by compromising on the board—maybe use a two-layer board instead of a four-layer board. That’s certainly possible but, again, you have to downgrade or degrade the performance because the two-layer board doesn’t have that many degrees of freedom in terms of performance. So cost is absolutely a critical part of the equation when you’re coming into designing not only IP but also when you’re looking at it from an SoC perspective.”

He believes a lot of engineers don’t quite understand these tradeoffs. While it is certainly possible to get the performance with a very expensive technology at 28nm with all the process options, all the different masks that allow all the different voltages, a nice package and an expensive board or connector, the reality is that many SoCs must be designed and manufactured in the cheapest possible environment.

“This could be the biggest mixed-signal challenge, because every six months or so engineering teams look at ways of getting the cost down on their product. But they want the performance, too, so the ingenuity from the engineering side really needs to apply to that: ‘How can I get the most out of very little in terms of the package, the board material and such,’” Nandra continued.

Complicating mixed-signal designs is the persistent drive for lower power, said Pat Hunter, product marketing engineer responsible for developing strategies for point-of-load power solutions at Texas Instruments. “Integration and power consumption [are trends,] but the biggest trend I really see is battery life because we all know—we’re consumers—the biggest complaint we all have about our cell phones is the battery life. In TI we do a lot in the area of charging the battery, but the more important part of it is accurately gauging the capacity of the battery.”

Low-power challenges in mixed-signal come from a couple of aspects, noted Cadence’s Nizic. “One is that we brought more digital into analog. Before we didn’t worry much how much of that digital was consuming because it was really small parts. If I have instead of a few hundred or a couple thousand standard cells now I have a hundred thousand or a few hundred thousands with my analog, that’s becoming a significant part of my overall power budget. Second, I want to use this digital to better optimize power of my analog — shut it down when it’s needed — it’s all interacting — now I have to apply low-power techniques on my digital part but at the same time, that complicates my interfaces with analog. That’s another dimension when I try to verify power modes and functionally entire design.”

Like Nandra, TI’s Hunter has seen customer demand for cost reduction, as well as the accompanying struggle to make the right architectural tradeoffs.

Speaking to designing devices for longer battery life, Hunter said, “If you look at them like they are fuel gauges, the biggest architectural tradeoff is you are adding cost to your system because the microcontroller will have an analog/digital converter on board and they can do their own gauging. But it’s very inaccurate because the batteries have internal impedance, and if you don’t keep up with internal impedance you’ll think that there’s less energy in the battery than there really is. I’ve got customers that were doing laser wrinkle removers and so they had their own A-to-D gauging the battery. They were doing a cost reduction. But the biggest complaint from their end customers (the consumer) was that they could never trust the battery reading. Here’s the case where they were going to do a cost reduction but they are adding my part because they needed that extra accuracy. The challenge is trying to justify the extra cost. The way you do that is with consumers. If you’ve got two smartphones side by side—they pretty much all do the same thing nowadays—but if you’ve heard this one’s got twice the battery life you as a consumer will buy that. Nobody cares that my solution is in there. They just care what my solution does for the product.”

When it comes down to it, cost defines everything. “It’s choice of process technology, choice of the IP that you’re going to use, speeds that you’re targeting, packaging, risks you’re willing to take. In the end, if you were to devote significant resources your quality would be great, but you have to make that tradeoff now between ‘my cell phone probably is going to be on the market for six to nine months before someone is going to expect an update or a new cell phone, so do I need to now run through all the qualification standards that require five years of operation?’” Nandra said.

By Ann Steffora Mutschler
Optimizing design methodologies for effective power utilization sometimes meaning throwing out old ideas and approaches and starting fresh. This is exactly what wireless chip giant Broadcom did in its quest to manage power in its chips. Low-Power Engineering spoke with Michael Hurlston, vice president of the mobile wireless group at Broadcom, to discuss current and future power challenges.

LPE: What are some of the business challenges of developing new low-power designs?
Hurlston: Wireless LAN chips originally were designed for applications like notebook computers, home routers and home gateways. In those particular applications, power was not so much a concern—maybe in notebooks a little bit—but I would say that the majority of questions we were getting from our customers had nothing to do with power consumption. Then in 2007 we got the crazy idea that maybe we could put Wi-Fi technology into ultra-portable applications like cell phones, portable games, iPods—things that were really battery-sensitive. As a result, obviously a focus from our customers was going to be on power. We had to at that time change our whole design philosophy to really focus on power. We ripped out our entire design methodology at that time and re-did it with a central theme of how do we get this power consumption out. There are a number of different aspects to power consumption. For a wireless chip there’s power while you are just sitting there in an idle state. There’s power when you’re transmitting or receiving—when you are actually active. And then there’s power that’s somewhere in the middle where you are kind of operating but you are really not. We had to optimize all three kinds of power consumption and rip out our entire design flow to refocus on power. That became a big challenge for us. In a wireless technology it’s all about balancing those demands: idle/leakage demand, active demands and then the quasi-on state, which we call sleep mode.

LPE: Specifically what did you change about your design flow?
Hurlston: A couple of key things changed that were very significant. In the old topology we had basically one power plane, which means that everything was operating off of sort of a universal power supply. One of the key architectural advancements we made was to do power islands and focus on things that were going to be ‘on’ at the same time by virtue of their operation. So rather than having one supply that is essentially running the whole chip we now have dozens. And each of the different power supplies is feeding a different part of the integrated circuit, and that power supply can then be turned on or off depending on whether that particular portion of the circuit is going to be needed for whatever operation is at hand. That was one thing. The second thing was to carefully architect the design to gate clocks going to areas that were non-essential for that particular operation. So rather than having the clocks indiscriminately fan out on the chip and then be running and toggling all the time we shut off clocks going to one portion of the chip or another. And the third advancement most specific to wireless LAN technology was bringing power amplifiers onto the chip. Any wireless technology needs some kind of power amplifier. Before that we were funneling our signaling off chip to an external power amplifier that we had very little control over. By bringing the power amplifier on chip we were designing in CMOS technology, which is a lower power technology than the BiCMOS or silicon germanium that was used for our external power amplifiers. We also were able to bring a tighter control loop between the power amplifier and the rest of the circuit, which allowed us to do some intelligent monitoring of the power amplifier and increase or decrease its output power. Obviously as you’re increasing the output power you’re increasing the power draw. We were able to create a feedback loop. Bringing those power amplifiers on chip was a very big benefit for us. We were the first company to be able to do that, and now it’s fairly pervasive in Wi-Fi technology.

LPE: Which foundries do you work with?
Hurlston: We have designs that are portable among four partners that we talk publicly about: SMIC, TSMC, Global Foundries and UMC. We feel like we are relatively unique where we can do one tapeout that is portable among those foundry partners and, depending on loading conditions in the fab, the pricing in a particular fab and a number of different factors we’ll ultimately steer a chip tapeout to one of those four. In certain cases, we’ll multi-source it where we will run the same device at two or more of those foundries.

LPE: What process geometry are your products manufactured with today?
Hurlston: Most of our products are at 65nm. We’ve announced as a company that we’re aggressively embarking on 40nm and that’s been a companywide shift toward 40nm. We are still shipping some of our older products in 130nm.

LPE: Do you ever run into issues with a single design between foundries?
Hurlston: Very, very rarely. It’s probably not fair of me to say, ‘none.’ You have to remember we are the largest tenant at three of those four foundries and among the top three at the fourth. So we definitely have the ability to get these guys to do some of the work for us. We have to do some of the work ourselves and try to come up with a common set of libraries and a common set of models that work across all of the foundries, but they are equally motivated to work with us. The goal is that our customers can have a board that would accept silicon from any one of those foundry sources.

LPE: When embarking on a new design, how much IP is being re-used?
Hurlston: Broadcom is interesting in that regard. We have a multi-layer model where first, we have centralized engineering—a central engineering team—and that central engineering team actually does things like phase-lock loops, analog-to-digital converters and power supply types of circuits. There are a whole host of things that they do and then farm out to all of the different chips that get done within Broadcom. All of the different businesses within Broadcom are drawing from that central engineering team and that gives us a tremendous amount of re-use. Even a wireless LAN block that my team is responsible for, we make it so it is portable among other chips so in the event that another business unit wanted to incorporate the wireless LAN function in a larger chip, they can very easily take our wireless LAN block and marry it to a larger system chip that they might be doing. We recently announced a chip like that where we took a DSL engine and it had a wireless LAN block inside. Our whole company is built up on IP re-use.

LPE: Looking ahead, what are the biggest technical challenges going to be in terms of developing for low power?
Hurlston: Obviously we are getting to a point where there are tradeoffs between lower and lower process geometry and leakage. I think the biggest thing that we get into now is standby power, which is somewhat inversely proportional to process geometry. Active power is directly proportional to process geometry, standby power is somewhat inversely proportional. In other words, as we go down in process node the leakage current goes up without a lot of extra precautions being taken. I would say that is the singular biggest challenge is how to solve this leakage problem.

Ignoring The Rules
In a classic example of how technology gets used in ways for which it wasn’t designed, the University of Massachusetts at Amherst has been experimenting with running embedded flash memory at voltages lower than what has been recommended by a microcontroller.

Using software algorithms the team at UMass’ Department of Computer Science has developed what it claims are reliable storage methods at low voltages without modifying the hardware. This is an interesting development, but it also raises lots of questions about how IP will ultimately be used.

The researchers presented a paper on the subject at the Usenix conference in San Jose, Calif., this week, and said the energy consumed was 34% lower using this method. The question for companies evaluating this approach is what effect it has on performance and security– and what the tradeoffs are in terms of area and cost.

Unifying Power Intent
Si2 has released version 2.0 of the Common Power Format in an effort to bridge the gap between CPF and the Unified Power Format (UPF). Just for reference, Cadence developed CPF while Mentor Graphics and Synopsys support UPF. Both try to define the power intent of a design, but interoperability has created problems—particularly at the verification stage for fabless companies that rely on third-party IP and specs.

Smarter Windows
Philips Research has developed an “e-Skin” panel that switches from black to transparent using scavenged energy from a mobile phone’s RF signals. Aside from just being interesting, it’s particularly useful for smart windows in an office building, which can be dimmed when the sun is bright and clear when it is not.

Reconfigurable radios
Imec has developed low-power spectrum sensors for cognitive radios and networks. This is the kind of technology that will mean fewer dropped calls, no matter where a phone—or more accurately, a communications device—is used.

–Ed Sperling

By Ed Sperling
Low-power is cool, but not necessarily cost-effective when it comes to automobiles.

A recent report from J.D. Power says that hybrids and electric-car demand is overhyped, with the big unknown being China. In fact, the combined sales of hybrids and battery-electric vehicles will total about 5.2 million units in 2020. That’s about 7.3 percent of the cars that will be sold that year.

J.D. Power entitled its report “Drive Green 2020: More Hope Than Reality” and bases its conclusions on a number of factors ranging from market trends, a lack of regulations and consumer sentiment—most notably sticker shock over the cost of these green vehicles.

What can change the equation is a spike in gas prices, some breakthrough that would reduce the cost of green cars, and a coordinated government policy. But the group said none of these scenarios are likely over the next decade.

And while that doesn’t impact the overall push for efficiency in vehicles with internal combustion engines, it does sound remarkably familiar. Haven’t we been here before with electric vehicles?

Cars aren’t the only green technology looking a shade more pale than before. Wind power turbine installations dropped 39% in the United States this year, due to lower prices for power and natural gas, according to a report by Bloomberg New Energy Finance.

While that’s a big drop in the United States, the overall industry numbers are expected to rise next year—in large part because of growing demand in China.

And finally, in the realm of why does this look so darned familiar, Pleotint is now making the first commercially available window film that works like the automatic tinting on automobile rearview mirrors. It darkens when it’s warmed by the sun. Pleotint was founded by Harlan Byker, who was instrumental in developing the self-dimming rearview mirror.

By Ed Sperling
The University of Washington and Georgia Institute of Technology have come up with an interesting concept for cutting the power needed for communication inside of buildings.

The approach is a new twist on wireline communications, which use the electrical wiring in a building as an antenna. That can save power because there is less distance for signals to travel, which means communication can happen at much lower power than using a whole-house or whole-building wireless router.

Signals still have to make their way throughout a building, though, which is why most of the past approaches use a mesh network, whereby nodes communicate with nearby nodes. Under the new approach, detailed in a white paper, only the base station receiver is actually wired to the powerline. The wireless signals are then routed through the powerline rather than through other nodes on the network.

The result is much lower power consumption because there is less distance to cover. Sensors only have to communicate with the nearest plug. It also results in much easier set-up by users and far less frequent battery changes inside of sensors.

The researchers also looked at the most power-intensive piece of wireless sensor nodes, the RF radio, and discovered that during communication the most power is consumed during receiving because it is always active. They substituted devices that could only send but not receive, with the brains of the operation centralized rather than distributed.

Will it catch on? Maybe. There are still some kinks to work out, such as data reliability and what happens at higher frequencies. But if battery life can be increased from months to years or even decades, convenience alone may make these kinds of systems much more interesting.

By Ann Steffora Mutschler
How do software application developers – even the ones sitting at home on their living room sofas with laptops – measure the power consumption of their application on the target device? This is a big problem today (something that is painfully obvious to owners of iPhones or Blackberries), and it will only get bigger.

Software engineers may think it is not their problem. They can write whatever code they want, then push off the issues to the hardware engineers who, in fact, have limited control.

To be sure, a hardware/software co-design environment is eventually going to be the ‘new frontier’ with models of abstraction used at higher and higher levels so that engineers can emulate certain applications or functions. And, of course, new tools will be needed to take these considerations into account. But from all accounts, those tools may still be years away from the engineers’ workbench, let alone the software development kit of the at-home developer.

Ideally, if high-level models can be created that break through the RTL descriptions of the hardware to the transaction level, hardware information can be captured and brought up to the software applications, whether that includes power consumption, software domains, or the like. Then engineers could see the impact of software and modify hardware accordingly, said Vic Kulkarni, general manager and senior VP of the RTL business unit at Apache Design Solutions. “Today it is the reverse: because you use whatever hardware is available and then software developers they don’t really have knowledge of what that hardware is capable of doing as such.”

Pete Hardee, director of solutions marketing at Cadence Design Systems noted that today’s smart phones, as convergent devices, contain about as much computing power as stand-alone devices had recently. “A smart phone today can easily contain the same processing power as mainstream PCs or laptops had maybe four or five years ago.” They contain video capabilities that would have been set-top boxes just a couple of years ago; high-definition video, and 3- to 5-megapixel cameras. At the same time, while we’ve had enormous leaps in the hardware technology, obviously still following Moore’s Law, the leaps in software productivity have actually outpaced Moore’s Law to make that happen on a mobile device. The thing it hasn’t outpaced is poor old battery technology. So despite all of this going on, we’ve still got lithium-ion batteries. Designers have done a great job to squeeze what they can out of them, but fundamentally we still expect to get through at least a full working day and get home and put the phone on charge.”

Granted, it does depend what you’re doing with the phone, but bottom line is that all of it is under software control. “When you’re analyzing power it’s not just about characterization of the hardware. You have to run with a significant number of system modes that represent the high activity of when I’m busy on all these various applications but also represent the low activity when I’m not busy, and also switching between those system modes so I can work out when it’s worth powering down parts of the device and when it’s not,” he said.

The challenge for many chip companies today is the need to simulate 30 different system modes. In addition, they are painstakingly measuring the bandwidth in all of those modes, in various parts of the chip and working out exactly how the power management system needs to cope: what can be slowed down, what needs to be sped up so it can be shut down for longer. All of these various modes need to be checked out. “Being able to measure the power in response to real system activity running real software becomes a big deal and there are very, very few solutions that can do that,” he said.

The prevalent thinking of today leans towards virtual platforms to do this measurement, but Hardee believes they are too abstract to be able to measure the effects on power. “As soon as you really need to look at the power scheme that is implemented in the hardware then you need to run at an accuracy which is going to slow down a virtual platform.”

To be fair, Cadence’s approach does include virtual platforms through its transaction-level simulators, and integration with the fast processor models from ARM and various other processor models available, but the company stresses its hardware-based emulation system for power-aware simulation.

Shabtay Matalon, ESL market development manager at Mentor Graphics, believes engineers already are familiar with the notion of abstraction—they started by abstracting gates to RTL and now there is an abstraction of RTL functionality at the higher-level writing using SystemC and transaction-level modeling. “People are aware that you can also abstract timing by creating a model that doesn’t contain all the information but has sufficient information to get the notion of timing. What people may not be aware is that we can create a model that can be used by the software engineer that contains an abstraction of power all the way up to ESL or TLM.”

This model associates power with the traffic flowing through these transaction-level models. Once those models get created they can be stitched together, Matalon said. The models can be of peripherals, of processors, or of devices, and can be stitched together to create a platform on which applications software can run.

Virtual platforms are the way to go at the very high-level, agreed Cary Chin, director of technical marketing for Synopsys’ low-power solutions group. “There are some pretty good ways to hook into the software stack through a virtual platform. But I still think that the connection from the virtual platform on down through to high-level RTL is still a little bit broken because there’s a lot of stuff that needs to happen to connect those environments together.”

The big question to answer here, though, is how much we want the software developer to be controlling the hardware directly, he said. It’s basically directly up against the idea of information hiding. “In a software development environment we try to hide things because there are things we can’t actually decide better at high-level versus a low-level. Those concepts come in exactly when you’re spanning software down into the hardware realm, as well, so it’s very hard to tell. You want to write software that’s really transportable between environments and things like that, but if you’re tied into closely to a particular hardware platform it makes that very difficult, as well.”

Educating the software developer
“With all of this, it would still be possible to write bad software that is very inefficient in the way data is used—maybe something that unnecessarily continually refreshes the LCD screen, for instance,” said Hardee. “How people get feedback for that really boils down to the application development kits that are provided by either the phone manufacturer or the network operator (Sprint has an application development network). On phones that use Android, there’s a development system. It would be possible to give people feedback in terms of bad optimization, bad memory usage, etc. in those development kits.”

Part of the solution may be an ecosystem or partnership approach, as well. “The idea of [EDA vendors] at some point partnering with somebody like Apple or Google to really extend their development kits down might actually make as much sense as trying to build stuff up from the hardware side because those guys have a lot of resources and they could actually help a lot in terms of meeting in the middle,” Chin added.

But that still doesn’t solve one of the big issues, which is the great divide that exists between the software and hardware worlds. “The chasm between hardware and software is bigger than the chasm between front-end and back-end design. The two worlds are not really well connected today and ultimately, if you think about it from the software development standpoint, there are different levels of abstraction in some sense that one can think about. There are high-level programming languages like C/C++, and then there is the low-level programming which is assembly code,” noted Will Ruby, senior director of product engineering and applications at Apache Design Solutions.

At least some of this can be dealt in the short term by using models, but some will also require new technology such as smart compilers.

“Assembly is actually closer to hardware but people typically don’t program in assembly unless they are doing embedded programming. Somehow the notion of hardware needs to be transported into a C/C++ or Java-type development environment. That’s where the models come in. We need models to represent the hardware behavior, but I think we would also need something like a smart compiler that can take advantage of some of these hardware hooks and understand that if you’re writing a program for a mobile application, you need to make some tradeoffs during compilation for performance or power consumption. People on the hardware side think about this all the time, but on the software side it’s not easy to do. So compilers may need to evolve in that direction. Compilers need to be hardware-aware and need to understand what hardware is doing,” he concluded.

By Pallab Chattejee
Just how much power can you squeeze out of a processor without destroying performance?

Ask IBM. The company introduced a new methodology for power and energy management on its multicore processor chips. The new PowerPC chip, the Power 7, has eight main processor cores each with its own L2 and L3 cache and two central memory controllers. The architecture for the design is built around an energy and power management schema called EnergyScale.

The EnergyScale system is a data-dependent, policy-based system that interprets activities in the processor cores, the memory hierarchy and the main memory. It is made up of four distinct parts: Sense, Decide, Control, and Actuate. The sense function is performed using both digital-thermal sensors (DTS) and critical-path monitors (CPM). The DTS utilizes 44 on-chip sense points that are organized as five per chiplet, emergency self-protect thermal throttling, and on the main memory controllers. The CPM detects circuit timing margin to help guide the optimal frequency and voltage adjustments.

The decide block is an off-chip, dedicated-function microcontroller that gets its information on the status of the chip though an EnergyScale I2C Slave communication port. To assist in the performance of the EnergyScale microcontroller, the system minimizes the communications bandwidth by packing the sensor data to reduce the number of read operations, multicasting the responses to reduce the number or writes and creating an automated on-chip transaction table which allows the sensor data to be streamed out in a single I2C command.

The control block features per-core frequency control ranging from -50% to +10% of the nominal frequency, on-chip support for off-chip voltage control, memory power management, and a command rate interface control. The core frequency control, in order to minimize latency, has an automated fast frequency slew of more than 50MHz per microsecond. The voltage control is done through a serial voltage I2C command interface, and is fully automated based on the policies that are defined. The memory management includes power-down modes for the DIMMs and also reducing the data access rate as needed. As the Power7 chip is an symmetric multiprocessing (SMP) system, and has SMP based memory interfaces, the command-rate interface control was built with asynchronous control to be as adaptable as possible while addressing the needs of any core chiplet.

The Actuate function uses three different power-down modes beside the normal operating mode. These modes are per-core, and are based on both levels of power reduction and latency to return to full function. The modes are “Nap,” which targets about 5 microseconds of latency to return to operation, and is structured on turning off the clocks to the execution units; “Sleep,” which features 1 millisecond of turn-on latency and which has the clocks shut off while also purging the local caches; and “Heavy Sleep,” which has a 2 millisecond target recovery time. In this mode, all the cores are in “Sleep” mode, and the voltage is reduced to all the cores, caches and the states are loaded into low-voltage retention registers. The exit from heavy sleep includes an automated voltage ramp back to full operating voltage as the hardware is automatically initialized. These energy policies are in addition to the per-core frequency scaling, and the associated core voltage scaling that goes with the frequency adjustment.

In addition to the direct sense, the firmware of the off-chip microcontroller can estimate functions based on the data coming in to adjust energy for leakage, temperature, and power supply variation. The last portion of intelligence for the energy-control system is the CPM. The circuitry dynamically detects margin in circuit timing and eliminates the potentials for static conservative margin guard-banding in the active designs.

The net result is more than a 50% improvement in the power for the individual cores as a system package using the automated on-chip controls and the off-chip microcontroller firmware based signal loop (as shown in the following figure).

Low-power radio stations in case of emergencies are becoming quite popular these days. Missouri City just bought one.
Apparently so are low-power WiFi spots, given the new round of funding that Ozmo just secured.

CNet just reviewed the battery life of laptop computers. What’s interesting is just how much the life of the battery drops off when companies go from 15-inch to 17-inch screens, while the difference on 13-inch vs. 15-inch screens is hardly noticeable.

On the research side, IMEC introduced a 4G radio that consumes as little as 40 milliwatts. That should make your smart phone last for substantially longer between charges.

By Ed Sperling

Hardware and software bugs are all around us. When an application suddenly dies or a smart phone freezes because of the unanticipated interaction between hardware and software blocks in a system on chip, most users aren’t even the least bit fazed. They usually just re-boot and forget about it.

Bugs caused by power are an entirely different matter, however. For one thing, they’re usually fatal. For another, they’re getting much, much harder to detect. And third, they’re harder to fix when they are detected.

“Debugging is getting much more difficult because when the lead generator is powered off, how do you find out that there’s a problem? You may have two power lines with a different Vdd because of connectivity and it will not work,” said Bhanu Kapoor, president of Mimasic, a consultancy focused on low power. “With power you used to have a single voltage. Now you have different supply lines, so you get new problems. Some of this can be detected in the netlist, but some of these problems also show up in the course of manufacturing.”

The problem is magnified by the addition of multiple power islands and multiple cores.

“Correct delivery of a power supply is at the core of many of the power issues, and traditional testing methods use a fault model that is based on wires erroneously connected to supply or ground,” Kapoor said. “And needless to say, incorrect delivery of power will result in fatal issues for proper operation of the chip. For example, an isolation cell at the output of a power domain ensures active regions receive meaningful signal when this domain is shut down. If the supply to the isolation cell itself is switched off due to either an incorrect wiring or improper placement of the isolation cell then active regions will see some unknown values that will lead to failure of operation in this mode. “

Similar things will happen if the power supply for a level-shifter has wiring issues. It may be worse here since depending upon of voltage differences, the issue may only show up sometimes. And there may be these very hard to find sneaky leakage paths that drain the battery much faster without any functional problem ever showing up. They will also sneak through testing methods and only show up as a fatal business issue.

Consider a real-world example: A major wireless chipmaker was recently headed to tapeout when it ran some additional tests and found eight bugs related to wrong implementations of power intent. “They would have caused catastrophic failures,” said Peter Hardee, director of solutions marketing at Cadence Design Systems. “Things are getting a lot more complex. You may have power domain ‘A’ physically separated from power domain ‘B,’ and at some point they need to talk. The problem is that the wires may run through power domain ‘C.’ Was ‘C’ on or off when you verified the chip?”

It’s not that the wireless chipmaker didn’t understand all of these issues, either. Even at the most sophisticated chip companies where power intent and design was part of the up-front architectural decisions, problems still surface late in the design cycle. A device may be functionally verifiable but have fatal errors. And there’s no magic button to push or even an integrated tools flow that solves everything.

“A lot of things that used to be secondary issues are now primary issues,” said Vic Kulkarni, general manager of the RTL business unit at Apache Design Automation. “In the past, you could just put a lot of margin into the design, but the voltage has to be high for that to work. Today, the margin is no longer there.”

Dueling priorities
Creating SoC designs has always been about making tradeoffs between area, power and performance. Before 90nm, however, the power was more of an afterthought than part of the initial planning process. At 65nm and beyond, it is now an integral part of every chip, along with software and IP—which also were afterthoughts at older process nodes.

“The reality is if you have a performance issue or a power problem, it stems from the fact that you may validated the hardware in isolation, but not in the context of the software application,” said Shabtay Matalon, ESL marketing manager in Mentor Graphics’ Design Creation Division. “There are ways to fix functionality in terms of software. But I’m not aware of one that can fix power or performance by fixing the software.”

IP is likewise a problem when it comes from multiple sources and when it involves multiple voltages. Big IP vendors are all emphasizing power-aware IP so that it can be re-used more easily. But the amount of IP inside all SoCs is growing steadily, in large part because there are too few engineers inside companies to re-invent that IP and still get a chip to market on time.

Not all of that IP runs at the same voltage, and not all of it is necessarily used in a manner in which it was intended by the IP vendor. And while power methodologies such as UPF and CPF are supposed to account for that, some of it still slips through the cracks. In the best-case scenario, some of that can be fixed with software. There are plenty of cases that don’t fit that description, however.

“The fatal bugs are the ones that kill the company before the product ships,” CEO of MCCI Corp. “What causes those are mask spins. Behind those are system-level problems. You hook it up to a critical system and it doesn’t work. It’s down at the PHY level or the RTL level and it’s not accessible to software.”

By Ed Sperling

The addition of multiple cores inside of computers has created an enormous opportunity for virtualization. Instead of running one operating system or one application, a single server or multicore PC can run multiple virtualized OSes on a single machine at the same time.

From the standpoint of energy efficiency, this has been a huge gain in data centers and the corporate enterprise. With most servers averaging 10% to 15% utilization, rather than the recommended 80%, one multicore serer running a virtualization layer could replace as many as eight less efficient single-core servers. That means less power to run applications, less power consumption by the new machines, and less power needed to cool server racks.

From an economic standpoint, this all makes sense. But that’s not the end of the road for virtualization. By the end of this year, that same technology will show up in smart phone prototypes, with products using this technology expected to hit the shelves in 2011.

“Our strategy has been that, over a period of time, mobile products would have a mobile interface,” said Srinivas Krishnamurti, director of product management and market development at VMware. “The goal is not just to shrink our existing technology to a mobile PC.”

Much of this has been under tight wraps since VMware bought Trango Virtual Processors in 2008. There has been much speculation in the mobile world about what all this means and how it will unfold, but little information. Details are now starting to emerge.

Krishnamurti said one use is allowing non-standard devices like the iPhone or Android device to be supported by corporate IT departments by using one of the cores for connecting to the enterprise. When that core is in use, access to other cores is restricted. But the next phases of development become far more interesting from a power-management standpoint.

Following the data center
Within the enterprise data center, one of the newer applications of virtualization technology is the ability to move processing onto machines, or even cores, that are underutilized and shut down any processors that are not in use. Entire regions of the data center can be shut down on weekends, for example, and loads concentrated where power is already being used. For a large company, that can result in savings of tens of millions of dollars annually.

In a mobile Internet device, that same strategy can be used to save battery. Lisa Su, senior vice president and general manager of Freescale’s networking and multimedia division, said the ability to partition for Linux and proprietary real-time operating systems opens up all sorts of possibilities for improving power management—particularly as more cores are added into the processors in these devices.

“Whatever we do at the infrastructure level will get down to the device level,” Su said. “We will see it on consumer devices soon.”

Taking full advantage of virtual machines in mobile Internet devices, however, requires that much of the power management be built into the software. A graphics-intensive application such as a game, for example, needs far more power than instant messaging. While those types of applications can be hard-wired into different sizes of cores with different voltages, allowing thyem to take advantage of whatever core becomes available with a virtual machine requires flexibility in the voltage supplied to the virtual machine running that application, regardless of what core it’s running on. There may be a fixed number of possibilities, or there may be a range of possibilities. So far, none of that has been fully worked out.

Also not fully worked out is how to verify the systems using this kind of technology. While virtualization has thrived in the enterprise, where machines are plugged into the power grid, handheld devices have had to rely on much more creative and painful techniques such as power gating, power islands and various on-off states. How virtualization will work with those states, and how devices will be verified, remains to be seen. For example, will virtualization supplant power islands altogether or be part of the strategy for turning parts of the chip on and off? And will virtualization ultimately require more power than power islands and right-sized cores with tightly coupled software?

Krishnamurti said VMware has been spending a lot of time on slimming down the hypervisor level in the virtualization layer, as well. The current layer for servers takes up about 32 megabytes of storage. In mobile phones, the new layer is expected to take up only 20 to 30 kilobytes. He declined to discuss more details, saying that VMware has a number of patents pending in this field.

“But from all the testing we’ve done so far, the power overhead is not significant,” he said. “The biggest drain on these devices is still the display.”