By Mark LaPedus
For some time, DRAM makers have been developing 3D memory chips, but commercial products still are not due out for some time because of technical and cost issues.

But the advent of the 3D DRAM era could be near the turning point, as two memory rivals have separately moved to bring their respective technologies closer to production. In one move, Micron Technology Inc. has disclosed the manufacturing flow for its recently announced Hybrid Memory Cube (HMC) technology, a 3D DRAM scheme geared for high-end servers and networking systems. Under the plan, IBM will manufacture the controller logic portions of the HMC within its own fab. Micron will make the memory portions, as well as assemble and test, the HMC devices within its own operations.

On another and more surprising front, Japanese DRAM maker Elpida Memory apparently has beat its larger rivals to the punch by announcing the industry’s first commercial Wide I/O DRAMs. The first device from Elpida, dubbed Wide IO Mobile RAM, is a 4 Gbit device based on a 30nm process technology and a 3D structure using through-silicon vias (TSVs). Elpida plans to sample its first Wide I/O DRAM devices this month. The devices are geared for next-generation smartphones and tablets.

Samsung Electronics Co. Ltd. and Hynix Semiconductor Inc. are also separately developing 3D DRAMs. The idea behind a 3D device is to stack existing die and connect them using TSVs, thereby lowering the resistivity and boosting the bandwidths. But the problems with 3D devices based on TSVs involve cost, technical issues and supply-chain headaches.

“There is a lot of attention and engineering resources being thrown at 3D right now by all DRAM developers, including Samsung, Micron, Elpida, and Hynix,” said Mike Howard, senior principal analyst for DRAM and memory at IHS iSuppli. “Wide I/O has yet to really reach a cost level that makes it competitive and we are likely still a few years away from mass adoption. Elpida may very well have a functioning part in the lab and may be able to produce test samples, but I think we’re still a few years away from this being used in anything but the most premium markets.”

Hank Lai, product planning for memory marketing at Samsung Semiconductor Inc., said Wide I/O DRAMs are not expected to gain traction until sometime in 2013. At present, smart phones and tablets are using plain-vanilla, low-power DDR3 DRAMs or mobile DRAMs based on the LPDDR2 interface standard. Before Wide I/O, the mobile market will move from LPDDR2 to the next-generation LPDDR3 interface standard, Lai said.
LPDDR2 has a maximum throughput of 8.5 Gbytes/second. LPDDR3 has a peak throughput of 12.8 Gbytes/second. Samsung claims its new LPDDR3 devices consume 20% less power than LPDDR2.

Elpida’s Wide IO Mobile RAM has 512 I/O pins. The device is said to achieve a data transfer rate of 12.8 Gbytes/second, roughly similar to LPDDR3. But Elpida’s Wide IO Mobile RAM has a height of 1.0mm, compared to 1.4mm with existing mobile DRAMs based on today’s package-on-package (PoP) technology.

Elpida acknowledged that the Wide I/O market will take time to evolve. The 4 Gbit Wide I/O DRAM will sample next month, but production “will take place sometime in the second half of 2012,” according to officials from Elpida. “For volume production, it will be sometime in 2013.”

In March of 2012, Elpida plans to sample a 16-Gbit DRAM, which is based on stacking four 4-Gbit Wide IO Mobile RAM chips. Mass production is due sometime after 2013, according to Elpida.

On the other end of the spectrum, Micron and Samsung are moving full speed ahead with HMC. “This is a slightly different product than Elpida’s and is targeted at server customers. The specs are very promising, but again, this is still a few years from hitting the big time—2013 at the soonest,” Howard said. “Samsung is also a part of the HMC group, lending weight to the product’s chances.”

In October, Samsung and Micron announced the creation of a consortium to develop an open interface specification for HMC. Micron is the actual designer of the HMC technology. Micron and Samsung, as well as Open-Silicon, Altera and Xilinx, are the founding members of the Hybrid Memory Cube Consortium (HMCC).

HMC will incorporate DRAM arrays stacked on a logic chip. The device is connected with 2,000 to 3,000 TSVs. HMC prototypes are said to clock in with bandwidth of 128 Gbytes/second.

It is not a widely known fact, but fabless ASIC house Open-Silicon is developing the controller IP for HMC. Colin Baldwin, director of marketing and business development for Open-Silicon, said the HMC controller will be based on the company’s Interlaken controller IP. Interlaken is a high-speed, chip-to-chip interface protocol that builds on the channelization and per-channel flow control features of SPI4.2. The Interlaken controller will serve as the interface between the memory and physical layer to help “boost the bandwidth” in the device, Baldwin said.

On the manufacturing front, the HMC device itself will go through a two-step process. The controller logic portion of HMC will be manufactured at IBM’s semiconductor fab in East Fishkill, N.Y., using the company’s 32nm, high-k metal gate process technology. IBM also will handle the TSV creation process based on Micron’s specifications.

Micron will develop and make the DRAM arrays in-house based on a 3xnm process within its own fabs, said Mike Black, a technology strategist at Micron. Micron will take the logic controller from IBM—and the in-house made memory arrays—and then will assemble and test the entire HMC device within Micron’s R&D production line in Boise, Ida, Black said.

Micron is in the qualification stage with the device. “We are feeling pretty good about it,” he said. “Most of the learning is done.”

By Ed Sperling
Samsung and Micron have joined forces to create 3D stacked memory, a development that has profound implications for manufacturing, packaging, design and power.

The fruit of their joint venture is the Hybrid Memory Cube—a hybrid of memory and logic—that comes in either four- or eight-layer stacks of memory. The logic layer is a memory controller that will work like a hypervisor for testing, routing and optimization.

The new device is a true 3D stack, including between 2,000 and 3,000 through-silicon vias. The die themselves will be manufactured at the 20nm process node or smaller, with an expected jump in throughput that will enable movement of the same amount of data for 70% less power, according to Scott Graham, general manager of DRAM marketing for Micron Technology.

Graham said the consortium will send invitations out to potential partners and that the specification for the HMC will be finalized next year. Still to be worked out is who manufactures the HMC. Both companies are expected to use different manufacturing facilities.

What becomes particularly interesting with 3D memory is the possibility of using the memory much more judiciously with heterogeneous cores so only the resources that are needed are actually used. That can save on power while also reserving enough performance for those applications that require more memory and processing power. These memories can be used both in 3D stacks, as well as 2.5D stacked configurations where the memory is connected through an interposer layer.

Both Graham and Pablo Temprano, director of DRAM and graphics marketing at Samsung Semiconductor, acknowledged there are numerous possible scenarios for using this technology. They noted that some customers also are looking at using 3D stacked memory to replace some of the cache on a chip because moving data in and out of memory can be extremely fast.

Intel working with solar power and 3D stacking
Intel Labs rolled out a novel concept this week—a new CPU architecture that it claims will offer five times the energy efficiency of other Pentium-class processors while offering the ability to run off a postage-stamp sized solar cell.

What’s unique about this approach is that the CPU drops below 10 milliwatts when its workload is load, but can utilize Intel’s burst approach to add in more cores when necessary. Bursting is akin to on-chip virtualization, in that it allows a single application to utilize any available processing resources.

Even more intriguing, though, is Intel’s collaboration with Micron on the latter’s Hybrid Memory Cube, which it claims will add a seven-fold improvement in energy efficiency over DDR3. In case you wondered whether Intel was experimenting with 2.5D and 3D stacked die architectures, this should provide the answer. The HMC is a 3D stacked die package, which greatly improves density and speed by adding multiple layers of chips connected with through-silicon vias. That both shortens the distance and widens the data pipes, while simultaneously requiring less energy to drive signals.

Most researchers look at stacked die as the best way to cut power while also improving performance. The fact that Intel already is collaborating with Micron on this approach opens up some interesting possibilities for the processor giant’s move into the low-power SoC world.

Lower power capacitors and transistors
Researchers at UC Berkeley are using a ferroelectric layer—in this case lead-zirconate-titanate—on an insulator to cut the minimum voltage needed to store a charge in a capacitor. By using this combination the charge can actually be amplified, creating negative capacitance and solving one of the big issues with capacitors.

The initial work was done at 200 degrees Celsius, but new materials are expected to allow this principle to operate at room temperature. They’re also working on putting these materials into transistors, which is where things get even more interesting. One of the big challenges in dropping the voltage inside of SoCs is the minimum needed to safeguard function and prevent data loss through gates. It remains to be seen whether amplifying a charge can actually alter the minimum voltage, but it’s certainly worth a try.

Perhaps even more interesting is who else is funding this effort—Semiconductor Research Corp. and the Office of Naval Research.

–Ed Sperling

By Ed Sperling
Semiconductor design always has been about solving technology issues one node at a time, often in the face of a perpetual barrage of looming problems. In fact, if there is any change at all, it’s in the number of threats that have to be solved now at each node, most of them driven by ever-increasing density and the laws of physics.

Stacking die holds the promise of becoming something of a game changer because it can solve multiple issues at once—power, performance, physical effects such as noise and crosstalk—while creating its own issues such as who’s responsible when two known good die don’t work in a package.

But the surprise among companies working with this packaging approach is that it’s harder to remove the heat from stacked die than anyone initially thought. The generally accepted premise that silicon is a good conductor of heat is true, but apparently not true enough. Early tests show that 3D stacks are showing some limits for through-silicon vias.

“What we found is that you have about a 7 to 10 watt maximum for through-silicon vias using current technology,” said Greg Bartlett, senior vice president of technology and integration engineering at GlobalFoundries. “After that you have to go to an interposer.”

This is somewhat counterintuitive, because most engineers have always assumed that 3D stacking would be the successor to 2.5D stacks. Unless something is done to change the technology, it may be the other way around. This is good news in one sense. It’s cheaper and easier to work with an interposer, which contains TSVs on a separate piece of silicon, than with TSVs running directly through stacked layers of thinner chips. There is less stress to deal with from drilling through a layer of silicon, and yield is higher if those TSVs are run through a thicker piece of silicon.

“The big problem now is that with a dense TSV the heat is trapped,” said Dian Yang, senior vice president of product management at Apache. “You have to use metal to dissipate the heat. People didn’t know the power density would be so high, and that has causes thermal issues that are much more severe.”

In 2.5D stacking, the tradeoff is the footprint. A 3D stack is much smaller and can fit into smaller spaces, which is why it has been of particular interest to companies such as Broadcom and Qualcomm.

It’s not the TSV technology itself that is causing problems. It’s the location of the TSVs. There are still places where TSVs work extremely well, such as inside of interposers and in stacked memory configurations. Memory is particularly attractive because it doesn’t generate heat anywhere near the level of logic. Micron and Samsung are both developing stacked memory configurations using TSVs and claim faster performance, higher density and lower power. This kind of memory can be used in a 2.5D as well as a 3D stack.

Other considerations are under way, as well, such as using different substrate materials using different cooling methods, such as microfluidics. But there will either have to be a compelling technology reason, which so far has not been proven, or a major ability to reduce the cost of these approaches before this kind of technology hits the mainstream. Until then, it’s anyone’s guess whether and for how long a pure 3D stacking approach will be successful.

By Ed Sperling

Portability Play
Synopsys is working with GlobalFoundries to deliver interoperable process design kits later this year at advanced nodes. iPDKs are particularly important for companies looking to use designs for multiple markets. A general-purpose process, for example, is critical for markets looking for higher performance, while low-power processes are important in applications where battery life is a differentiating factor.

The problem is that many of these designs are not always portable between processes, despite the fact that power and performance are considered tradeoffs in most designs.

The companies said the 65nm G and enhanced low power (LPe) kits are available now. Versions for other process nodes will be available later this year.

Stacked die demo
Imec, the Belgian research organization, demonstrated a stacked die with DRAM on logic at Semicon this week. The chip is a prototype of what is expected to become a mainstream approach as companies seek to re-use existing analog IP and subsystems from previous nodes, as well as to add flexibility and speed to complex designs.

What’s particularly interesting about the prototype is Imec’s description of how heat can be removed from the die. Logic generates a fair amount of heat, but the DRAM die acts as a conductor for some of that heat. Qualcomm observed similar effects in its own stacking research last year.

Imec’s work was done in conjunction with GlobalFoundries, Intel, Micron, Samsung, TSMC, Fujitsu, Sony, Amkor and Qualcomm.

By David Lammers
The trends towards vertical transistors, non-silicon channel materials, and resistive RAMs promise to hold center stage at the 2010 IEEE International Electron Devices Meeting (IEDM), set to begin Dec. 6 in San Francisco, Calif. (www.ieee-iedm.org)

Taiwan Semiconductor Manufacturing Co. (TSMC, Hsinchu, Taiwan) will present a 22/20nm technology platform based on a FinFET architecture. The TSMC paper describes a full CMOS technology, complete with silicon germanium stressors, high-k/metal gate, and dual-epitaxy technology. TSMC said it demonstrated a 0.1µm2 SRAM cell, which operated at a 0.45V operating voltage (Vmin) with a 90 mV noise margin.

While TSMC is expected to shift from today’s planar transistors to the vertical FinFET devices at the 14nm generation in the 2015 time frame, the IEDM 22/20nm paper demonstrates that the world’s leading foundry has the FinFET manufacturing challenges well in hand. TSMC used 193nm immersion lithography to achieve NMOS and PMOS drive currents of 1200/1100 µA/µm respectively, at off-currents of 100 nA/µm.

Fig. 1: TSMC will unveil a complete FinFET-based 22/20nm CMOS logic technology at IEDM 2010. Electron microscope images show a cross-section of the vertical fin’s sidewall.

While creating 20nm gate-length vertical transistors is “demanding,” due to parasitic capacitances and other challenges, an abstract of the TSMC paper said the FinFET architecture allows continued scaling with good electrostatic control of the channel. To accomplish its scaling goals, TSMC turned a series of process technology knobs, including embedded SiGe to strain the PMOS channel, stress memorization techniques in the NMOS devices, an optimized contact edge stop layer (CESL), dual work functions, and both epitaxial silicon and boron-doped e-SiGe in the source and drain regions. Compared with planar transistors, the TSMC paper will describe much (100x) improved leakage from the source and drain regions, critical for low-power mobile systems.

Intel and IQE Inc. researchers will describe their latest advances with a FinFET architecture based on an InGaAs quantum well technology. At the 2009 IEDM, Intel described a surface-channel InGaAs FinFET. The quantum well InGaAs FinFET features fins, which are 35nm-wide and smaller, 5nm gate-to-drain and gate-to-source separations, and a high-k gate dielectric.

Intel and its research partner have been developing quantum-well compound devices as successors to silicon CMOS. The paper to be presented at the 2010 IEDM takes the InGaAs technology from a planar to a FinFET architecture, which delivers much-improved control of the channel compared with the planar devices described at the previous meetings. Also, the paper describes a high-k dielectric with a Tox of 20.5 Angstroms and good interface properties.

An InGaAs MOSFET will be presented by a team led by the University of Tokyo. The device features a 3.5nm channel, the smallest such device to be described thus far. The dual-gate device was created on a silicon substrate using wafer bonding.

Memories taking resistive turn
On the memory front, researchers from Intel and Micron Technology have developed a 25nm multi-level cell (MLC) NAND memory technology, with a cell size of 0.0028 µm2 – the smallest transistor now in production. An air gap was introduced between word lines to control the word line-to-word line capacitance and cell-to-cell interference.

The MLC device uses only 30 to 40 electrons per level, which requires advancements in the insulating tunnel oxide and the inter-poly dielectric in order to confine the charges. The cell has an asymmetric design, with a word line half pitch of 24.5nm and a 28.5nm half pitch in the bit line direction, allowing for insertion of the control gate between the floating gates. The technology is used for 64-Gbit NAND memories.

The authors will describe how the Intel-Micron team dealt with dopant fluctuations, structural bending, and other challenges presented at such small dimensions.

Fig. 2: Researchers from Intel and Micron Technology will describe the 25nm 64Gbit multi-level cell (MLC) NAND technology. The image shows the select gate and contacts in the bit line direction.

Resistive RAMs (RRAMs), which use a voltage to alter the resistive state of metal-based compounds, have emerged as a path to higher-density non-volatile memories once NAND flash scaling reaches its limit. A functional transition-metal-oxide resistive memory (TMO-RRAM) developed at the National Nano Device Laboratories in Taiwan has a record 9nm half-pitch, with a programming current of less than 1 µA, which compares with about 20 mA for phase-change memories. The researchers controlled the device’s resistivity by changing the chemical composition of the tungsten-oxide layer. They postulate that the memory’s change in resistance is due to the controlled movement of oxygen ions, with a monotonically varying ratio of oxygen and tungsten atoms.

The Taiwan laboratory’s research team includes Chinming Hu, a professor at the University of California, Berkeley. In an abstract of the paper, they said the “unexpectedly low” 1 µA current required to set and reset the RRAM cell makes it a promising candidate for low-power non-volatile memories.

The reported progress with exploratory RRAMs comes amid concerns about power consumption with the phase-change RAMs (PC-RAMs), which use heat to change the resistive state of a chalcogenide material. At IEDM, a team from the IBM/Macronix PCRAM Joint Project will describe a previously unknown failure mechanism for phase-change memories, apparently related to electromigration stemming from the polarity of the operating current.

At the high current densities required to change the state of the chalcogenide material, the researchers found that hole-induced electromigration occurs when current polarity is reversed. The paper claims that the phenomenon causes voids at the interface between the phase-change material and the bottom electrodes, limiting their cycling endurance by four orders of magnitude. The team also will discuss countermeasures to deal with the effect.

IBM researchers also will describe their latest-generation SOI-based embedded DRAM (eDRAM), enhanced with a high-k/metal gate technology. Big Blue claims eDRAM delivers several advantages over SRAM for large on-chip caches, including higher density, better soft error rates, and lower power consumption. The performance rivals SRAM speeds, with the SOI eDRAM delivering a sub-1.5ns latency and 2ns cycle time.

The 32nm eDRAM uses a deep trench capacitor with 25 percent higher capacitance and much less resistance than conventional memory stacks based on SiON/poly gate stacks. IBM said it use of a high-k/metal gate technology to reduce leakage and control the threshold voltage of 40 mV. IBM created a 32 Mbit array from cells measuring 0.39 µm2. The eDRAM is 3-4x smaller than a comparable SRAM, enabling a much-higher density on-chip cache, the abstract of the paper said.

By Pallab Chatterjee
With the release of the EnergyStar rating for servers, there have been a number of approaches to meet the requirements for increasing density and performance. Standards communities such as JEDEC and the 40G/100G networking associations are currently finalizing adoption of the Isolation Memory Buffer (iMB) technology for new high-performance memories.

The use of this technology creates a new class of memory module called the LRDIMM, or load-reduced dual inline memory module. This technology was developed by Inphi, a 10-year-old high-speed analog semiconductor company from Sunnyvale, Calif.

The key issue for modern data centers is how to address growing performance needs while decreasing power budgets. LRDIMM technology is supported by a custom logic controller chip that handles buffering through a standard load interface. The key is a high signal integrity-based memory buffer that has a fixed load to the bus independent of the memory depth behind it. This allows configurations that would be using one bank of memory to support up to eight banks of memory in the same speed and bus power. For compatibility and optimization with multicore CPUs, the iMB interface includes task-based duty-cycle reduction and deep memory idle states.

The iMB parts use dynamic termination of the memory banks to manage power for DDR3 operation at 800, 1066, 1333 bus speeds at both 1.35v and 1.5v operation. These features are also supported through the new JEDEC 1600 spec and will be scalable to DDR4 3200 applications.

The LRDIMMs will be built in Q1 by Hynix, Samsung, Micron, Naya and others using the Inphi chips. The products are currently only for enterprise-class EnergyStar applications as the Inphi chip that is being used costs about $25 in quantities of 100,000. The advantage of the technology is the power reduction and density/performance improvement while still maintaining the 10-12 BER and supporting a single chip/single cycle load for both command and address signa