By Pallab Chatterjee
Low power and connectivity are the two pervasive design constraints for chips and systems being designed today, and they are showing up in devices that have not had architectural changes in decades. Some of the changes are customer-driven, some are consortia-driven, and international cooperation is making some of the regulatory-driven.

The regulatory side is moving slowly, but it is making progress. The state of California started an advanced power limit program for TVs that initially was expected to be the death of plasma TVs. However, designers have met the challenge, and along with technologies to create larger displays they have developed many new products including plasma TVs within the power limit. In fact, the plasma TV market has been staging a comeback, both in the consumer products and digital signage applications.

LCD TVs, meanwhile, have been adjusted to being dominated by LED backlighting from CFL. This has led to innovations in light-guide technology, new quantum dot technology to allow for color clarity from lower-power LED sources, and new edge film that reduce the number of LEDs needed to backlight a TV. These regulatory changes for TV have now spread to the same technology being used for computer displays without additional state or federal guidelines.

Also on the regulatory front, the set-top box (STB) and over-the-top boxes (OTT) have finally been noticed. STB devices currently do not have a power down or off state. They are on 100% of the time. The box consists of an RF-in processing section, a tuner, remote control and transcoder logic, local processing for a channel guide information to be formatted and displayed and an output RF processing section. Since a number of these blocks are not needed when the channel is not changing or the associated display device is off, power down features are coming to these boxes.

The remote control sections will go to a keep alive and search for signal structure, along with full function modes. Similarly, when a single channel is selected, then only one mode of the tuner and transcoder will be selected and set. When the TVs are off, then the RF sections are powered down. The power consumption for a typical dual-HD STB with DVR can be as high as 70W. New generation technology (power down, standby, digital tuners, etc.) utilize about 17 to 20W. SD non-DVR receivers can use upwards of 42W, while new designs are near 14W. These are now being covered by the EnergyStar guidelines.

On the committee side, the Energy Efficient Ethernet guidelines are an integral constraint on most of the new 10G, 40G, 100G and 1T standards. The PHY designs are being optimized for low latency (microsecond range) turn on from power down. These are for both electrical and optical interconnect styles. The MAC have to be able to deal with the modified packet streams, changes in block size and also support higher BER requirements on the order of 10 (-16). To handle the power constraints these systems are also handling the duality of needing new materials for smaller higher-speed backplane connections while handling longer cable interconnect lengths (up to 10Km from 2Km lengths).

The consumer side is still driven by the battery constraint based on viewing video content. Nirvana for the mobile product is to be able to display a high-definition image (something 480i or better) uninterrupted over the duration of a standard 140-minute movie or 195-minute sports broadcast. The channel has not been able to really take advantage of the improvements in battery technology, as the energy consumption from higher-resolution graphics and the power required for receiving streaming content has consumed those advances.
The first realization is close, with some tablet devices having sufficient storage capacity to hold a movie, as transferred via a powered cable, in the low-power SSD storage and do the playback without the RF being on. Some of these systems have exhibited 2.5 hours of playback capability with stereo sound.

By Ed Sperling
The number of factors required for an effective power model has far surpassed the capabilities of even the most detailed spreadsheet at 45nm and beyond. It has now entered the realm of complex databases and architectural tradeoffs, and those tradeoffs will become even more complex as 3D stacking takes root over the next 24 months.

The idea of modeling power is hardly new, but you wouldn’t know that comparing the current iterations side-by-side with the old methods. While there is still a need to understand worst-case scenarios to protect signal integrity, not to mention the other components on a chip, there is far more that needs to be considered in power modeling at advanced nodes than in the past.

“There are two issues that need to be solved,” said Ran Avinun, marketing group director for system design and verification at Cadence. “One is how to do this. The second is who owns the format. The methodology hasn’t been solved yet. When you tell the customer that we’ll compare our numbers with your back-end flow and libraries, that’s not good enough. It’s going to give me the data about the SoC or the ASIC, but that’s not enough. When customers look at power it’s what they measure in the lab. When they test the device it’s in a real environment with real software and the package. Today they don’t have a good way to test. It’s done with software and vectors, but it’s not really reflecting what the user will get.”

The second issue is understanding what parts of the system actually consume power. “Customers don’t know how to partition the power consumption of the ASIC vs. the overall system, so what they measure is the overall power. They don’t know how to partition those components and there is no good way to model that. We’re looking at the ASIC and die level, but they need to model the whole system,” Avinun said.

Moreover, for the system-level numbers to be used in a meaningful way at the architectural level they have to be relatively accurate. The shrinkage of components has made everything more susceptible to the effects of power, mechanical and thermal stress, electromagnetic interference, electromigration and noise (see fig. 1). Modeling power is now required. But even the simplest ideas such as power supplies are no longer simple.

Fig. 1. Source: Apache Design Solutions

“In the past we had two power supplies, one for the digital and one for the analog,” said Cornelia Golovanov, an EMI expert at LSI. “Now we have three or four analog power supplies in a small area, which makes the supplies very inductive. These are not well analyzed in the context of the whole system.”

Like anything else at advanced nodes, without adequate planning power supplies can be corrupted. Even maximum power, which used to be calculated in a worst-case scenario fashion once RTL was already synthesized, has become incredibly complex with multiple power islands, multiple modes, multiple cores and multiple voltages.

“With a power model ideally you want to cover all scenarios and all vectors,” Golovanov said. “But some of these have really long simulation points. It can take weeks at the end of the design cycle, and then you have to factor in the chip in the package on the PCB. There is no time for that.”

What’s in the model?
That’s where models fit in. Much attention has been paid to the different library approaches for defining power intent with the Unified Power Format (UPF) and the Common Power Format (CPF). The power model is a level above that, defining the power delivery network, signal integrity analysis, electromagnetic interference and compatibility (EMI/EMC) and the thermal effects of power, primarily in the form of dynamic and static leakage.

“In the past power models were simplistic in nature and deemed sufficient for the needs at that time,” said Aveek Sarkar, vice president of product engineering and support at Apache Design Solutions. “You could provide a single current and single capacitance and the result was your best guesswork. That all began to change in 2006 when we moved to 65nm. The package design could no longer be off the shelf. It’s now a competitive difference for companies and it can determine the price and performance of a system. Hence, an accurate model that represents the actual activity and parasitic profile of the chip is important off which you can base package and PCB decisions.”

Packaging has other issues, though. While a chip consumes current, the package and the PCB can act as an antenna for chip-generated noise, which results in EMI. It’s becoming necessary to extract an S-parameter model (scattered parameter) model for the package. Once that model is constructed, then a full system-level AC, DC, and time-domain analysis, then a full analysis can proceed using the power models of the chip, said Sarkar.

“Right now 40nm is mainstream,” he said. “At 22nm and 28nm electromigration gets very complicated. Since electromigration and leakage current can change very drastically with a temperature increase, we have to model the thermal profile of the chip–especially for a stacked die configuration.”

But there’s also a point where models can become useless. Looking at everything from a very high abstraction level is excellent for layout and functionality, but it can insert some very large errors into power models—sometimes as high as 300%, according to Cadence’s Avinun.

And there needs to be more consistency among models to make them useful. Frank Schirrmeister, director of product marketing for system level solutions at Synopsys, said the standards don’t yet exist because this is all so new.

“In TSMC’s reference flow 11, they characterize their libraries for low power and then make this all accessible for TLM 2.0 modeling,” Schirrmeister said. “Then you should be able to add up meaningful power numbers, even at the system level. Today this is all in the early stages. The different vendors have different formats. At some point it needs standardization.”

Standards needed
All of the major foundries are working on these kinds of models. In addition, Apache is working with the GSA on models for power. Those will become particularly useful in stacked die configurations, where thermal issues are not always intuitive. (See fig. 2)

Fig. 2. Source: Apache Design Solutions

None of this will get solved quickly. For one thing, power models generated by memory makers may be different than those generated by foundries and IP vendors, which is where standards will become important. But the first step is creating a dialog and generating tools that can provide visibility inside and SoC, and so far at least that seems to be happening.

By Colleen Taylor
With a job that can legitimately count “the inherent constraints of quantum physics” as a major cause of workplace stress, engineers in the semiconductor industry have never exactly had it easy. But as policymakers focused on curbing emissions impose increasingly strict regulations on the power consumption of consumer electronic devices, a host of new challenges have emerged for chip designers.

In coming issues of Low-Power Engineering we’ll be taking a look at how some of the industry’s newly enacted standards and regulations—and others waiting in the pipeline—will continue to impact chip design in the years to come.

Ethernet
Low-power idle features are now required for most consumer electronic devices, but the Ethernet switches that deliver connectivity to those devices have remained woefully inefficient. According to an August report by the IEEE’s Juan Antonio Maestro and Pedro Reviriego, the hundreds of millions of Ethernet links installed throughout the world today consume a sizable amount of energy even when they are not transmitting data. With worldwide Internet usage showing no signs of slowing down, Ethernet has become one of the highest priority areas for today’s efficiency-minded technology standards boards.

A few years ago the IEEE set about tackling Ethernet’s power problem by forming an Energy-Efficient Ethernet (EEE) task force aimed specifically at reducing network energy usage by implementing low-power idle features in Ethernet devices. In early October the IEEE officially announced the ratification of 802.3az, the specification developed by the EEE task group, and last week the specification was formally published.

According to EEE task force chairman Mike Bennett, 802.3az was developed as an attempt to get in front of the Ethernet power consumption problem before government regulators began imposing their version of standards on the electronics industry. “The European code of conduct was starting to look at DSL and broadband-type links, and EnergyStar already had some incentives for computer systems and that sort of thing, so it’s only natural at some point to start looking at the network,” Bennett said. “I had a visionary colleague in the 802.3 group who said, ‘We need to do something before we’re told to do something. We can develop a solution that we want, or we can have regulators come in and tell us to do it.’”

Early feedback from chip designers working with the 802.3az has been positive, Bennett said. “Anecdotally, we’ve received very positive feedback. We did a panel on EEE at a conference earlier this year, and there was a system designer who commented on how he was able to get a prototype up and running fairly quickly.”

Designers working with the spec should experiment with taking advantage of 802.3az’s low power idle features and the layer 2 capability that comes with it, Bennett said. 802.3az includes the ability for widely-adopted BASE-T and BASE-K physical layer components to be able to be put into a low power idle while using the layer 2 link layer discovery protocol (LLDP) specified in IEEE 802.1ab and 802.3bc standards.

“The layer 2 capability that comes with EEE allows link partners to communicate how long it takes to go from asleep to awake,” he noted. “So if a designer would like to be aggressive in terms of power savings, if the PHY is asleep, he or she can also go turn off things in the system that don’t have to be running if the PHY is asleep and set parameters to make those things stay asleep longer.”

When 802.3az compliant-products have been fully deployed in new and existing Ethernet networks, the IEEE estimates that power savings in the United States alone can reach 5 terawatt-hours per year. That’s enough energy to power 6 million 100-watt light bulbs. Chip designers will set the pace for the timeline on which wide-scale deployment of EEE-compliant devices will take place. “We know that some network equipment vendors have already placed EEE on their roadmaps, so we know it’s coming. At this point, it’s just a matter of how quickly the chip designers can get products in the market,” Bennett said. “I’d be comfortable with guessing that within the next five to seven years, we’ll see a significant portion of the current Ethernet devices being replaced with low power ones.”

But while the challenges of working with 802.3az are sure to keep chip designers busy for the time being, engineers would do well to keep one eye on the horizon for new low-power Ethernet developments that are sure to come. For instance: While the new EEE specification will significantly improve the energy efficiency of 10Gbps copper transceivers, one study suggests that designers can achieve even better results if they look beyond the copper PHY status quo. According to a paper presented at the National Fiber Optic Engineers Conference in May 2010, optical Ethernet devices with fiber PHYs are more energy-efficient than 802.3az compliant copper PHY devices.

Bennett noted that the EEE task force chose to focus its first specification on devices with copper transceivers simply because most organizations are heavily invested in copper infrastructure. “We got the low-hanging fruit taken care of first,” he said. But the task force has been keeping abreast of the opportunities presented by optical Ethernet, and could well hold an informal discussion about the technology at the next 802.3 plenary session to be held in Dallas next week. “My personal opinion is [low-power optical Ethernet] ought to be studied,” Bennett said. “But generally, copper products are lower cost, and until the economics of that change, we won’t see a purely optical network for some time.”