By Ed Sperling
It’s no secret that designing SoCs is getting tougher, but what’s surprising is just how far behind the existing EDA approaches are lagging.

The result is a growing gap between what’s needed and what’s available to do the job. In a presentation at the Tech Design Forum in Santa Clara, Calif., yesterday, Shabtay Matalon, Mentor’s ESL market development manager, said there is a 55% growth in the number of transistors per year compared with a 21% annual growth in productivity.

Much of this gap is in the consumer electronics space, where the demand for better performance and more functionality is coupled with longer battery life. Among design teams surveyed by Mentor, 61.8% are currently developing single-processor SoCs, while 20.8% are developing multiprocessing SoCs, and 5.2% are developing chips with multiple cores and multiprocessing.

Fast forward two years from now and the expectation is that only 30.1% of designs will use one processor; 20.6% will employ multiprocessing; 21.4% will use multicore technology and 19.4% will use multicore and multiprocessing technology.

“There is a gap between the power requirement and the power trend,” said Matalon. He said that if the power is allowed to trend upward at current rates it will far exceed the amount that’s permissible in designs.

“At the same time, you have to deal with software and verification and account for the power requirement,” he said. “There are two verification challenges that need to be solved. One involves design goal challenges where you meet functionality with speed, power and cost. Power is one of the biggest risks today because it’s evaluated at the end of the design. The second challenge is multicore and multiprocessing designs. If you wait until you get to the back end of the process it’s too late.”

All of the big three EDA vendors have been issuing similar warnings over the past year, saying that after 45nm it becomes increasingly difficult to build complex SoCs without electronic system level tools. While the exact node has been somewhat in flux—the numbers vary between 65nm and 45nm, sometimes even within the same chipmaker or EDA company—the message is essentially the same. And all agree that at 28nm and beyond understanding transaction-level modeling and automating some of the analog design and verification is no longer an option.

TSMC and GlobalFoundries have been working with all the major EDA companies on incorporating ESL models into their flows. Tom Quan, deputy director of design methodology and service marketing at TSMC, said that Reference Flow 12 is being developed that will incorporate 28nm, 22nm and 3D stacking. The new flow heavily leverages ESL tools, which are a critical part of design for manufacturing.