By Ed Sperling
While most of the semiconductor industry wrestles with what to do after 40nm, at least the number of options is increasing—they can move to 28nm or 20nm using bulk CMOS or fully depleted SOI; they can stack die in 2.5D or 3D configurations, leveraging analog that was considered bulletproof at older technology nodes; or they can move to 14nm using finFETs and double patterning.
While these kinds of decisions are largely business-related, what’s becoming clear is that the technology is progressing rapidly enough to make all of them viable options. All can improve performance, reduce current leakage, and be used to lower overall power consumed by a chip.
The tapeout of a test chip by ARM, Cadence and Synopsys at 14nm using finFETs is a case in point. The chip is based on a Cortex A7 processor and Artisan standard-cell libraries, and was designed using Cadence’s Encounter platform and Synopsys’ DesignWare embedded memory IP. On top of that, Samsung tapped Mentor to provide its Calibre DFM suite, Tessent DFT tools, and other DRC technology, which are essential for obtaining adequate yield.
Each of the Big Three EDA vendors issued press releases within a 24-hour period that ignored their rivals, but the real story is that a test chip and a full suite of tools now are available for the 14nm process node using Samsung’s process. That process also should be compatible with processes from both IBM and GlobalFoundries, which are part of the Common Platform initiative with Samsung.
Intel, which is ARM’s chief rival, has already begun manufacturing finFETs using its bulk CMOS process at 22nm. Intel currently is preparing to roll out 14nm next year, and currently is working on 10nm. STMicroelectronics, meanwhile, has introduced FD-SOI chips at 28nm, and IBM is working on finFETs using an FD-SOI substrate.
Nor is Samsung the only foundry working on this technology. TSMC and UMC are both developing finFET technology, and GlobalFoundries is working on both FD-SOI and finFETs.