By Ed Sperling
While most of the semiconductor industry wrestles with what to do after 40nm, at least the number of options is increasing—they can move to 28nm or 20nm using bulk CMOS or fully depleted SOI; they can stack die in 2.5D or 3D configurations, leveraging analog that was considered bulletproof at older technology nodes; or they can move to 14nm using finFETs and double patterning.

While these kinds of decisions are largely business-related, what’s becoming clear is that the technology is progressing rapidly enough to make all of them viable options. All can improve performance, reduce current leakage, and be used to lower overall power consumed by a chip.

The tapeout of a test chip by ARM, Cadence and Synopsys at 14nm using finFETs is a case in point. The chip is based on a Cortex A7 processor and Artisan standard-cell libraries, and was designed using Cadence’s Encounter platform and Synopsys’ DesignWare embedded memory IP. On top of that, Samsung tapped Mentor to provide its Calibre DFM suite, Tessent DFT tools, and other DRC technology, which are essential for obtaining adequate yield.

Each of the Big Three EDA vendors issued press releases within a 24-hour period that ignored their rivals, but the real story is that a test chip and a full suite of tools now are available for the 14nm process node using Samsung’s process. That process also should be compatible with processes from both IBM and GlobalFoundries, which are part of the Common Platform initiative with Samsung.

Intel, which is ARM’s chief rival, has already begun manufacturing finFETs using its bulk CMOS process at 22nm. Intel currently is preparing to roll out 14nm next year, and currently is working on 10nm. STMicroelectronics, meanwhile, has introduced FD-SOI chips at 28nm, and IBM is working on finFETs using an FD-SOI substrate.

Nor is Samsung the only foundry working on this technology. TSMC and UMC are both developing finFET technology, and GlobalFoundries is working on both FD-SOI and finFETs.

By Pallab Chatterjee
As mobile platforms become a larger part of the component spectrum, their need for optimization beyond low power has moved to the forefront.

Traditionally, standard “line-cord” based products in both the consumer and commercial sectors have used the “G” label processes from semiconductor foundries. These processes had the highest-yielding combination of design rules, device performance and leakage as a tradeoff triad. The “G” processes were then further split into the “HP” and “LP” flows. The “HP” processes are high-performance optimized with the most aggressive design rules, lowest Vt, and support standard to higher operating voltages. The “LP” processes are optimized for low power and feature design rules targeted for the lowest leakage, support lower operative voltages, and tend to have the slowest transistors of the three options.

These process labels have been the industry norm from the 250nm era through the 40nm processes. At 28nm and below, a new process is emerging called the “HPL” or “HPM” process. UMC offers an HPL flow, which is a high performance and low power dual-corner optimized technology. At TSMC, the newly offered HPM flow is for high-performance mobile applications and is also optimized for high performance and low power.

The complexity of SoCs for mobile applications has driven them to use cutting-edge processes. The rise of computing visualization and content playback has forced these extended battery operation cycle products to embrace multicore architectures with embedded memory as the main design. To accommodate these activities, along with high-performance graphics handling, the designs have moved to single die SoCs, which minimize I/O as a method to reduce power.

These multicore designs also feature advanced power management based on switched power controls and a controlled state-based turn-on/turn-off of the power grid to different power blocks. Power-switch devices, with the ability to have very large devices to minimize the “on” resistance, are typically not optimized for high-performance processes. The new flows allow these devices to be built, along with high-performance processor and graphics cores, with significantly lower leakage than on HP flows.

TSMC announced the new flow earlier this month as a specialized optimization for battery operation, low-operating voltage, low leakage, and high-speed logic and memory access at the 28nm and 22nm nodes. The mobile platforms are driving enough of the wafer volumes to warrant a specialized flow rather than a “mix and match” from the other processes. The driver is not only smart phones, but also netbooks, tablets and other platforms that will consume graphic content. This content is spit between gaming applications and video/TV material. The video/TV material has the additional power optimization point of RF for the streaming connection to receive the content. The gaming content tends to reside locally on the platform.

This new process optimization also is driving new IP. The I/Os typically are migrating over from standard LP processes, as there is no major change to the external world. However, high performance IP is not applicable to the new flow. The basis of the new IP is power control and operation in a power envelope. From this constraint, the performance optimization is then imposed.

Companies such as Imagination Technologies, which feature soft IP, will not have any major issues with optimization to the new process offering. However, hard processor cores, cache memories, DSP’s, graphical user interfaces and display controllers will have to be redesigned. These blocks will need to incorporate the power-switching logic into their design, and support native multi-voltage blocks.

With UMC and TSMC offering these processes for foundry, and Intel and Samsung having them as internally use new processes, it won’t be long before GlobalFoundries and the Common Platform bring this new optimization point to market.