Guidelines For Designing Multi-Voltage ICs
By Arvind Narayanan
Multi-voltage designs are increasingly common in ICs for mobile devices, but can be difficult to implement. The design flows for multi-voltage architectures are inherently complex and present many new challenges because many blocks are either operating at different voltages or are shut down intermittently.
Multi-threshold CMOS switches enable switching off certain portions of an IC when that functionality is not required, and then restoring power as needed. Specials cells, such as level shifters and isolation cells, need to be used on nets that cross domain boundaries if the supply voltages are different, or if one of the blocks can be shut down independently. Best practices are beginning to catch up with the demands of multi-voltage design, and using the latest tools that incorporate these practices can make the difference between taping out the design on time and within specification, and facing the consequences of a late or underperforming product.
As we all know, any complex problem can be broken down into smaller problems. The ten steps presented below represent a simplified multi-voltage flow for physical design of low power ICs. However, before embarking on a multi-voltage design adventure, the system architects must be positive that multi-voltage is indeed the best option. Can the power budget be met through the use of multiple threshold cells or clock gating? Is it better to use hardware or software partitioning? If so, then stick with those techniques. If not, arm yourself with the latest information, and proceed with caution through the methodology below.
Ensure that the architecture is frozen and captures all the power constraints required for the chosen multi-voltage style in the IEEE1801 Unified Power Format (UPF) file (Figure 1). A little extra time spent in capturing the power intent in UPF can pay off by avoiding implementation and verification problems later in the flow. After reading in the power specification, users can analyze domains and power connectivity with queries to the design tool database. Users can trace connectivity on power pins just like on signal pins, verify the power applied to a given pin, and check isolation cells, level shifters, switches, and retention cells. The UPF file includes the power state table (PST), which defines the combinations of voltages and power states, which can be essentially treated as operational modes in the design environment.
RTL verification and synthesis
Using the UPF file, perform thorough power-aware functional verification. This will uncover any functional bugs, including failure to retain state information, improper sequencing, reset failure, activity in OFF states and, occasionally, an unexpected ‘always OFF’ condition. Ensure that the simulation and verification runs are complete and validated, since errors here will lead to painful engineering change order iterations. Complete RTL synthesis and derive the gate level netlist.
Next convert the netlist to a GDS implementation (i.e., a physical layout). Begin by importing all the standard physical design files—including LEF, .lib, SDC, Verilog and DEF—for the given design. Properties that are relevant to the multi-voltage design flow include:
• Special cells in the library, including ‘always_on’, ‘is_isolation_cell’, ‘is_isolation_enable’ and ‘is_level_shifter’ attributes.
• Process corners and design modes for the different power domains. Ensure that the worst-case timing and power corners are setup correctly to optimize concurrently for power and timing.
• Floor plan updates including the regions that map to the power domains to the physical boundaries; when assigning cells to a region, leaf cells or wildcards should not be used, instead, logical hierarchies should be assigned to the region.
Power domain setup
Read the power domain definition by sourcing or loading the golden UPF file (the same one that was used for RTL synthesis). After reading the UPF file, the following items will be defined:
• Domains with default power and ground nets;
• Power state table (PST) to define all possible power state combinations; the PST captures the valid interaction between the different domains so the tools can determine the optimal buffering strategy;
• Level shifter and isolation rules for the different voltage domains;
• Power or ground switches for domains that are shut down.
Floor planning and placement
The physical implementation tool should automatically instantiate voltage islands as regions with physical boundaries and create the power mesh for each supply net defined in the UPF (Fig. 2). It also should insert special cells automatically for voltage islands and power shut off regions, including isolation cells, level shifters, multi-threshold CMOS switches, always-on buffers and state retention cells. The designer needs to define domain-specific hierarchy mapping and library association based on the architecture. The placer should group cells into the partitions and assign partition pins.
Power domain verification
This is a critical step to ensure that the power constraints are defined properly and to avoid last minute surprises. Perform multi-voltage checks for general design and UPF setup, and verify that level shifters are inserted on all the nets crossing different voltage domains and that isolation cells are inserted on floating nets for domains that are shut down. Analyze always-on connections to ensure that the signal is buffered correctly.
Design tools can automatically perform power domain verification and design checks for general design and UPF setup, verification of level shifters and isolation cells, and analysis of always-on connections. Tools also can do general checks for common setup issues or missing data after loading a design and defining the power domains. The intent here is to help users find any missing UPF or power domain setup data that could lead to non-optimal results and lengthy iterations. Figure 3 shows a typical power domain verification report.
Pre clock synthesis optimization
During the pre-clock tree synthesis flow, ensure that no port punching (duplicate ports) occurs on power domain interfaces. The optimization engine in the design tool should use the power state table when buffering nets to choose between always-on buffers and regular buffers automatically. For example, if feed-through buffering is enabled and a net between two domains requires a buffer, but the buffer physically needs to be placed outside of the domains the net connects, the tool should place the buffer physically outside of the two domains and add it logically to the hierarchy of the driving cell. This will prevent logical port punching but still allow an optimal buffering solution. The power supplies for the new buffer will be determined based upon the PST buffering algorithm.
Clock tree synthesis
Like the optimizer, the clock tree synthesis engine should use the PST-based buffering solution while expanding the clock tree network. Some clock tree synthesis flows require special clock gate classes to be recognized in order to restrict sizing operations to equivalent class types.
Whatever the specific requirements of your flow, the results can be improved by using a multi-corner, multimode (MCMM) aware flow. Because each voltage supply and operational mode implies different timing and power constraints on the design, multi-voltage methodologies cause the number of design corners to increase exponentially with addition of each domain or voltage island. Additionally, the worst-case power corners don’t necessarily correspond to the worst-case timing, so it’s virtually impossible to know how to pick a set of corners that will result in true optimization across all design objectives without excessive design margins. For example, Figure 4 shows how the corners and power states proliferate for even a simple multi-voltage design. The core operates at 1.2V or 1.8V. One power island operates at 0.9 to 1.2V and can switch on and off. The second power island operates at 0.9 to 1.5V.
In order to close the design across all modes, corners, and power domains, the setup and hold times must be analyzed simultaneously for different combinations of library models, voltages, and interconnect (RC) corners. Each timing and optimization pass would require multiple RC extractions, timing analysis runs and power analysis runs, which increases the engineering effort during the final stages of the chip implementation.
The best solution is to analyze and optimize the design for all corners and modes concurrently. In other words, low-power design inherently requires true MCMM optimization for both power and timing. MCMM considers power domains, modes and corners simultaneously to reduce functional skew and to balance skew across corners. The end result is that the design should meet timing and power requirements for all the mode/corner scenarios.
The router should honor the domain boundaries and contain the routes within them. Secondary power pin connections for special cells should adhere to special properties set on the power pins. Many design flows also require double vias and non-default width wires for routing of the secondary power connections. Top-level nets that span across domains can be handled using ‘gas stations’ to help optimize timing and area. Gas stations are mini islands, used for buffering signals that pass through domains that are powered down, especially useful for very long nets. Since the gas station has a constant power supply, regular buffers can be used to drive the top-level nets. Gas station methodology helps minimize top-level congestion by efficiently routing top-level nets, thereby improving timing.
After routing and post-route optimization, timing and power analysis will let you know whether the efforts invested in steps 1 to 9 have paid off. If they have not, you may need to go back to the architectural planning stage. If they have—congratulations! Proceed to design rule check and design for manufacturing analysis and signoff, then tapeout to GDSII.
Using multiple voltage domains is the most effective method of achieving the lowest possible power, but this strategy adds several new requirements to physical design flows. Success with multi-voltage requires careful planning at the architectural level and a robust methodology and toolset for all stages of the implementation. Once established, however, the multi-voltage approach enables the development of ultra-low-power ICs and SoCs for the rapidly growing wireless segment.
—Arvind Narayanan is the Olympus-SoC product marketing manager for Mentor Graphics’ place and route group.