Don’t Be Afraid of the Dark
By Barry Pangrle
I had the opportunity to attend the Hot Chips conference at Stanford in August and not surprisingly power was an important theme of many of the presentations. IBM had a presentation on adaptive energy management for their POWER7 chip, and Inphi presented on cloud computing without power penalties. Presenters from the Institute of Computing Technology at the Chinese Academy of Sciences gave a talk on a high-performance low-power XPU, and AMD presented information on their new Bobcat x86 architecture that’s been specifically designed for low-power applications, to only name a few.
A presentation that really caught my attention was: “GreenDroid: A Mobile Application Processor for a Future of Dark Silicon,” presented by Nathan Goulding from UC San Diego. For readers who haven’t previously heard of “Dark Silicon,” it’s a phrase that was coined by the CTO of ARM, Mike Muller. It plays on the expectation that as we go from 45nm to 11nm technology, that the design density will increase by a factor of approximately 16 and clock frequencies could over double, inferring that on a per device basis we would need a reduction of about a factor of 40 in power just to stay where we are today. Unfortunately, the predictions are that we’ll get about a 1/3 reduction on a per device basis. Mike Muller has said this implies that only about 9% of the transistors on the chip could be activated, leaving large portions of the chip “dark,” hence the term dark silicon.
What are the implications of such a prognosis? Well for one, it will certainly impact the way chips are designed, but that’s probably not an unmanageable situation. Certainly if someone had told designers 10 years ago that we were quickly approaching the end of the exponential increase in clock frequencies and that for many designs clock frequencies would drop or remain flat, that news wouldn’t have been greeted with cheers. Importantly though, it hasn’t meant the end to higher levels of integration and more performance gains. So, if the predictions are correct, and in terms of the direction the probability is high that they are, then we know that: 1) we won’t be able to activate as much of the on-chip functionality simultaneously and 2) on a functionality basis, the cost of silicon will be cheaper.
The GreenDroid researchers are using this information to look for portions of the design, especially those in software, that use a lot of power, replacing them with more efficient implementations in hardware. In other words, go from a more general-purpose and less energy-efficient implementation into a more specific and more energy-efficient implementation that, oh by the way, is going to take up more space on the chip and will probably only be used when that specific functionality needs to be executed. So in summary, the new approach uses: 1) more chip area, 2) typically isn’t used all of the time so that it can be shut off more frequently and 3) reduces energy consumption. Overall it looks like a pretty good idea given the trend.
The next question is, “What kinds of tools are needed to be able to efficiently convert algorithms written in software into hardware?” If you were to ask me, I’d say that ESL and HLS tools are targeted at solving this very problem. Again, this all ties back into the ITRS 2009 report calling for more of the design power savings to come from the use of higher-level tools. It appears that they’ll also be needed for making better use of all that chip area so that we won’t have to be afraid of the dark (silicon).
Last month I left readers with the question: How many universities are there in the Big Ten and how many are in the Big 12? The Big 10 currently has 11 universities proper (not going into the CIC and the University of Chicago) and will expand to 12 when Nebraska (Lincoln) joins the conference in July 2011. The Big 12 currently has 12 universities but is scheduled to drop to 10 when the University of Nebraska leaves for the Big 10 and the University of Colorado leaves to join the Pac-10 (which will also get the University of Utah, so we’ll have another conference with “10” in the name and 12 universities). A Rose Bowl by any other name…?
Now, for a bonus number mix-up, and I’m even part of it. The question was: how many ISLPED conferences have been held. The answer is: 15. ISLPED 2010 CDs are labeled as the 16th. Oops. It turns out that the first ISLPED was held in 1996. Prior to that, two conferences, ISLPE and ISLPD were both held in 1994 and 1995. Some bad data somewhere along the way led to an off by one error. Special thanks to Professor Jan Rabaey from UC Berkeley for straightening out the history of the conference. Thanks to everyone who attended in Austin this year. The registration was up by about 30% over last year and there were many excellent keynotes and presentations.
–-Barry Pangrle is a solutions architect for low-power design and verification at Mentor Graphics
Tags: Mentor Graphics