By Barry Pangrle
Applied Materials announced its latest version of nano-porous low-k dielectric technology called Black Diamond 3 last month at Semicon West. What really caught my ear though was the marketing claim that 1/3 of total chip power consumption (really energy) is in the interconnect.
I thought about this a bit, and certainly for some designs this seemed to easily be quite possible. The paper referenced though was published back in 2002 and it made projections about where chips would be in 2011. But hey, why use nine-year-old projections when we can easily find chips fabricated in 2011.
Bill Dally, in his 2009 DAC Keynote entitled, “The End of Denial Architecture and the Rise of Throughput Computing,” had a slide “Moving a Word Across Die.” Bill points out that performing one 64-bit floating point multiply accumulate (FMA) operation will consume only half the energy of moving the three operands and result in 1mm on the chip (or in other words, twice the energy is spent moving the data compared to the actual computation). If the data is stored farther away from the computation unit it gets worse, and if the data is off-chip it’s much worse. So there’s clearly something to keeping an eye on the energy consumed in the interconnect from a process as well as an architectural standpoint.
There’s more to process development than just gate stacks and transistor design. Applied’s new material has a dielectric constant (k-value) of about 2.2 compared to about 2.5 for the previous generation Black Diamond 2 and about 3.0 for the original Black Diamond. Black Diamond is still used at 90nm and 65nm nodes, and Black Diamond 2 for 45nm to 32nm. The newest version is targeted for 28nm down to 14nm. A briefing available here contains the diagram shown below.
So, the new material appears to be approximately 12% lower in terms of the dielectric constant than the previous Gen 2 material and almost 27% lower than the original Black Diamond, and this should lead to a directly proportional reduction in the dynamic power. From a first order standpoint, if 33% of the power is in the interconnect then this leads to roughly a 3.6% reduction in overall power from BD2 and 9% from the original BD. The total savings could actually be even higher by using smaller drive gates and buffers to drive the smaller resultant parasitic loads. If a higher proportion of the power is in the interconnect then the savings will be even greater. In addition to its better dielectric properties, the new material also includes improved strength properties. It looks to be a very welcome breakthrough by process and design engineers alike.
–Barry Pangrle is a solutions architect for low-power design and verification at Mentor Graphics.