Interconnect Power II
After submitting last month’s blog, I read a very interesting article by Deepak Sekar analyzing Intel’s 22 nm FinFET technology versus a hypothetical planar 22nm CMOS technology. Beyond the advantages of being able to use a 140 mV reduction in the supply voltage for the trigate technology, Deepak did a breakdown analysis for the predicted power across a representative microprocessor mobile logic core design. Deepak also references a SLIP’04 paper entitled, “Interconnect-Power Dissipation in a Microprocessor” by Magen et. al., describing results for the analysis of a Intel Pentium M processor (0.13 um with 77 million transistors) with more detail shown in their presentation. The first two pie charts below are from Magen’s SLIP’04 paper and the last bar-chart is from Deepak’s article.
The analysis for the Pentium M includes a detailed breakdown for the dynamic power. The authors model three types of capacitance; interconnect (metal wires), gate (actual gates of the MOS transistors) and diffusion (the effective capacitance of the junction between the diffusion region used to form the source and drain and the well or substrate).
As can be seen in Chart 1, most of the dynamic power is used in the Interconnect, which shouldn’t be too surprising. The astute reader may also be wondering what happened to the short-circuit (or crowbar) power. The authors claimed that it was later added by using an overall factor of about 10% and that the focus of the paper was on energy dissipation due to the switching of interconnection capacitances (gate and diffusion included).
Chart 2 shows the total dynamic power used for clocks and signals both locally and globally. In this case, 58% of the dynamic power is in the signals and 42% is in the clocks. It should be remembered though that this part was designed as an efficient “low-power” processor and that higher performance parts could easily have a higher percentage of power in the clocks. Jan Rabaey has a nice chart in slide 1.30 of his book, Low Power Design Essentials, showing the variation in clock and logic power over four different processor designs.
So we’ve had a chance to look at some data from an older processor. How do things shape-up when projected to 22 nm? Clearly, a big chunk of the power is still in the clock and wires, and this seems to hold whether we’re looking at trigate or planar transistors. It looks like the reduction in the dielectric coefficient for the interconnect layers will still be welcomed at 22 nm. Another interesting point about the projected approximately 28% power savings in the trigate versus planar transistor is that Deepak used a source voltage of 0.82 V for the planar devices and 0.68 V for the trigate devices. Doing a straight V-squared analysis would yield about a 31% savings in dynamic power alone. This may indicate that it still leaves the door open for a planar process that could further improve on process threshold variation enough that it would enable the source voltage to also drop further.
–Barry Pangrle is a solutions architect for low-power design and verification at Mentor Graphics.