Intel’s Claremont Near-Threshold Voltage IA Core
By Barry Pangrle
Intel announced many new technologies at its recent Intel Developer Forum (IDF) held from Sept. 13-15 in San Francisco, but the one announcement that jumped out at me was the unveiling of its work on a near-threshold voltage (NTV) processor named “Claremont.” For this exercise, Intel chose an older Pentium design to help minimize the number of variables the engineers would have to deal with in order to get the chip working at the voltage levels they were targeting. Intel CEO Paul Otellini mentioned the Claremont chip in his keynote and then CTO Justin Rattner’s keynote (minutes 46-53) went into more depth with Shekhar Borkar and Sriram Vangal also taking the stage to help with the demonstrations. Sriram has also provided more information about Claremont in his blog.
It has long been known that reducing VDD leads to significant energy savings, but there are numerous issues with pushing the supply voltage near-threshold levels. The threshold voltage of a transistor is roughly thought of as the gate voltage relative to the source voltage where a transistor turns “on.” In fact, CMOS transistors are not perfect switches and current flows even before the threshold voltage is reached and this is often considered an undesirable effect. For example, sub-threshold leakage current is typically thought of as an undesirable characteristic of CMOS devices.
Designing memories becomes more challenging and the use of differential sense amplifiers that typically sense about a 100 mV difference become less effective as VDD decreases to near-threshold voltages. Claremont is reported to run at voltages as low as 400 to 500 millivolts. Another challenge to running at such low voltages is the variation in the threshold voltages of the transistors themselves on a chip. If the variation is large enough and the supply is very close to the nominal threshold voltage, some transistors might actually fall into the sub-threshold range, adversely impacting the timing of the design. Overcoming these challenges to produce a working x86 processor design at near-threshold voltages is a significant accomplishment.
The slide shown below from the Justin’s keynote presentation diagrams an energy efficiency curve over a range of operating voltages.
While the slide shows approximately a 5X gain in efficiency that matches Intel’s results with Claremont, Shekhar Borkar had claimed about 8X possible gains using NTV. Shekhar explained that the results showed only a 5X gain due to the use of an old Pentium architecture. In fact, the Intel engineers had to go “dumpster diving” and looking on eBay to find motherboards that would work with the chip. Again it’s interesting to note the impact that the architecture makes on the overall energy efficiency of the design. Shekhar later clarified that ~8-10x should be possible with architectural improvements.
Another important note about this chip was that it was also designed to work at higher voltages and frequencies. Claremont can run at clock frequencies that are 10x of those at near-threshold voltages, giving it a dynamic range capable of running at much higher performance levels and then dropping back down to very low power levels. The demonstration showed Claremont running on a small solar cell and at a claimed power of less than 10 millivolts, all in all a pretty impressive display. While Claremont is a proof of concept vehicle and won’t be sold as a product, expect to see the fruits of this research showing up in future Intel processors.
-–Barry Pangrle is a solutions architect for low-power design and verification at Mentor Graphics.