There is a very close correlation between power and complexity in an SoC. The more functionality that is required to meet market demands, the greater the need to push to the next process node in order to fit it all onto a single die. The result is more power density, and more attempts to limit the effects of that density with power islands, different voltages, gating, and a variety of other techniques.

Two of those techniques have received a fair amount of attention. One is dynamic voltage and frequency scaling. Rather than using a set voltage, the voltage can rise and fall as necessary depending upon the compute task to maximize efficiency. This already has been proven in processors, where the technique is relatively well established.

A second technique is near-threshold computing, whereby compute operations are performed even before a processor is fully powered up, and may even shut down before it’s fully operational. Intel executives have talked about this on multiple occasions, and it may be a useful tool in very regular layouts.

But these approaches are becoming far less interesting for SoC developers, including those at the advanced process nodes. The reason is the growing complexity of power-related issues. It’s hard enough to come up with power estimates and power budgets for components in an SoC without having to build in sliding scales on top of those numbers, and it’s almost impossible to achieve good coverage and signoff on a chip whose power numbers fall into a distribution rather than hard numbers based upon well-defined modes of operation—on, off, and various stages of sleep.

The solutions that seem to be gaining the most traction for energy efficiency focus more on partitioning of processing and functions into independent subsystems—or at least quasi-subsystems—so there is less contention for memory, and less difficulty in verifying and characterizing them. That also makes it simpler to divide and conquer the engineering for a complex SoC, and it provides more manageable fixed numbers for dynamic power, leakage, and thermal modeling.

The focus on power clearly isn’t decreasing. In fact, quite the opposite is true. But the best choices for what makes the most sense for bringing a working chip to market quickly, on budget, and within acceptable power limits are shifting. While some of the most advanced techniques make sense at 40nm, or with certain types of chips, the advent of fully depleted SOI at 28nm and finFETs at 20nm renders them far less attractive in comparison. They can severely impact time to market and greatly increase the number of unknowns that make verification more difficult.

It’s not that engineers can’t make these miraculous advanced power-saving techniques work. It’s that they can’t make them all mesh on a densely packed and incredibly complex SoC in the amount of time they’re allotted. And if something has to go, the logical choice is more uncertainty.

—Ed Sperling

For the past few years, EDA companies have been warning chipmakers that power will become the biggest issue they face at future nodes. They were right.

While it may not be the only big problem—after all, the number of issues at each new tick of Moore’s Law is growing—power is certainly one of the most challenging and by far the most pervasive. In fact, the warnings about just how pernicious a problem it has become are beginning to resemble the famous Far Side cartoon about objects in the mirror being closer than they appear.

There are some important technology advances in this space. Fully-depleted SOI is one. Stacked die, particularly in 2.5D configurations, are another. 3D-IC are still a work in progress.

FinFETs are further along, and the advantage is that they reduce leakage at the gate. What they don’t do is reduce power density—particularly dynamic power density. The result is that thermal measurements taken at the bottom of tens of millions of tightly packed finFETs are different than measurements taken at the top. And as more metal layers are added into die, heat becomes a recurring issue for which there is no easy answer—similar to the problems researchers are wrestling with in stacked die configurations.

That’s only part of the problem, of course. Thin wires create their own source of heat. And densely packed SoCs are prone to electromigration and electromagnetic interference. Add in more power islands and there are enough unknowns to affect signal integrity, power integrity, and the functionality of an SoC.

The question now isn’t how to deal with these problems. Smart engineers can devise solutions to just about anything, given enough resources. If there isn’t more time, throw more engineers at the problem and amortize the cost over the life of a chip or derivative chips. If they can’t solve the problem with simulators, give them access to emulators. And if electrons ultimately become too difficult to work with, as IBM predicts, there are options with optical communication.

But power is unique because it affects everything. It’s not a single problem. It’s an addendum to every other problem and the cause of entirely new ones. And the only way to get a grasp on its magnitude is to understand how interactions of formerly separate areas of design can affect power. What’s needed is a giant model of everything, so that it can be verified and signed off with confidence. This is an enormous task, and it means integrating an understanding of power into well-established design flows, from architecture through to manufacturing. And even then, there is still the nagging concern that software downloaded from the Internet can ruin a lot of hard work.

What is becoming clear as we move forward is that none of this can be solved by any single company, no matter how large or advanced. It has to be solved by an ecosystem working together on solutions, standards, and sharing information. Even worse, it has to be solved yesterday. While tools vendors may see this as a golden opportunity, the opportunity will be far greater if everyone works together—not something for which EDA is always a shining example.

The upside for dealing with power effectively is huge, and the market will continue to grow as mainstream chipmakers begin encountering some of the same issues that giant chipmakers in markets such as mobile phones and computers have been wrestling with for several process nodes. Even the Internet of Things will require a deep understanding of power-related issues. And in the future, so will everything else, including those attached to an energy source with a plug.

But there’s also a potential downside in a high-profile failure—the proverbial $100 million mistake. That would reflect badly on the entire industry, including those who had no part in that failure. There’s a lot riding on cooperation when it comes to power. The entire industry has to roll up its sleeves and work together to get this right. The clock is ticking.

—Ed Sperling

The Internet of Things raises some interesting questions that have never been fully addressed in semiconductor design. For instance, how do you assess the necessary performance for any particular thing? And how long is another thing willing to wait for information to be passed along?

These sound like fairly basic engineering questions—until you consider that the Internet of Things is actually a giant system rather than a bunch of individual devices functioning in isolation. A good proxy is the transition from television receivers to the so-called smart TVs. A television receiver simply has to be able to download content, and the wait time or the picture quality depend on what’s inside the TV. A 120Hz TV consumes less power than a 240Hz TV, and a faster internal processor generally uses more energy than a slower one.

A smart TV is a different story, though. It receives and it transmits, and the more it transmits the more it impacts the power and performance requirements of the network-based communications system. This may seem negligible for one TV, but multiply that times hundreds of thousands of TVs all streaming video, uploading information about quality, speed, protocols and other TV-based information, and the relationship between power and performance becomes much more complicated. It takes longer to wait for a slow processor to communicate, and depending on the configuration of the network-based system, that could require a significant increase in power.

The Internet of Things will have a number of similar types of tradeoffs, except the universe of devices communicating back and forth will be even more diverse. That begs the question, how long should a thing wait for a communication to be completed, and how long should the receiver wait for a thing to communicate to it? All of this affects power of the device and of the system in which it operates—at least some of the time.

And we are only at the beginning stages of this next phase of development. If people can be spammed, marketed to and plagued with viruses, so can things. A refrigerator that has a digital readout that shows milk is expired can communicate brands of milk and the benefits of one brand over another. The perfect machine for an owner does only what it’s supposed to do. That maximizes efficiency.

The perfect machine for an OEM does a lot more than that, providing a potential gateway for information of all sorts, with less regard for the overall device’s efficiency, its impact on network traffic, or the total system energy consumed. Moreover, that data can be mined at any time, which is why the National Resources Defense Council issued a report back in June 2011 that DVR, cable and satellite boxes are wasting $2 billion in electricity each year.

The Internet of Things, constructed properly, can keep the incremental costs to a minimum. Done wrong, it can escalate to many times that number. And given how regulations typically lag technology by years, if not decades, it’s highly probable that more waste is on the way—with very little anyone can do about it.

—Ed Sperling

If finFETs work as planned, it’s likely they will show up in every complex SoC for decades to come. Adding another dimension to transistors has enormous potential at advanced nodes, and maybe even at older nodes.

3D transistors also could be part of stacked die, and they can be combined with fully depleted SOI—two other options for reducing power. Moreover, it’s likely that whatever GlobalFoundries, TSMC and Samsung agree upon is what most fabless companies will utilize. And while companies may not move to the most advanced nodes as quickly as the foundries and EDA companies would like, they will use the latest technologies for controlling leakage current if they’re commercially proven, cost-effective and readily available as part of a complete solution.

FinFETs still have to prove themselves on all three counts, however. And no matter how large the hype factor, that’s a big challenge.

To begin with, test chips are not commercially available chips, and Intel processors—the first to commercially employ finFETs—are not SoCs. Intel’s processors are very regular structures with very regular layouts, shapes and well-defined rules. That makes for much more predictable yields.

For finFET-based SoCs, yield isn’t so simple to determine. It may be solvable with current tools and approaches. It may not. We don’t know. And we don’t know how lithography will affect yield and cost. EUV, which was slated as the replacement for 193 immersion technology at 45nm, now appears to have missed the 10nm node window. What is the technological viability of a quadruple-patterned finFET with 14nm back-end of line process? Will yields be within expected parameters?

Second, how much will it cost to really develop these chips? We are standing on the precipice of a new technology that has to deal with the same kind of power density issues as the previous planar technology. While getting the heat out of stacked die is a known problem, thermal patterns are far less well documented with tightly packed finFETs. These are like mini towers on a substrate that can trap heat, which can affect power budgets. Leakage is certainly reduced at the gate, and there is a potential for reducing voltage. However, there are still the same RC issues with interconnects and wires, not to mention noise.

These are solvable issues, but they cost money to solve. Companies like Intel, IBM, Apple and Samsung command a premium for their processors, which means they can absorb the costs for these new technologies. If new chip technology can save data centers millions of dollars in electricity costs per year, it’s worth every penny of investment. Likewise, if those chips will be sold in volumes of hundreds of millions of units, the cost can be amortized more easily. But how about a run of 10,000 chips or even 100,000 chips? The economics are vastly different.

Third, all of this work is just beginning. Planar transistors have been subject to decades of intensive and incremental engineering work. 3D transistors are brand new. And while they may be a major breakthrough in all respects, it will take time to understand all of their quirks, to automate the design and verification flow, and to improve the manufacturing and cost equation.

This is interesting technology with huge promise, but prime time for its rollout will depend on the market, an individual company’s tolerance for risk, and a lot of unknowns that have yet to be discovered.

—Ed Sperling

By Ed Sperling
The number of options available for reducing power and improving performance are increasing for the first time in a decade. This is good news for chipmakers. It’s far less clear who stands to benefit on the tools, IP, capital equipment and manufacturing side.

Choice is always a good thing in design. It allows teams to trade off one IP block for another, based upon the needs of a particular application or even a single design, and to weigh one approach versus another in everything from layout to memory configuration. Will it be sold in huge volume or into markets where price isn’t an issue—think data centers, for example—or will it be used in a highly competitive consumer device?

Even Moore’s Law seems to be bending slightly to accommodate all of this. The work on directed self-assembly is making huge strides, which could make it a reality at 10nm or 7nm if extreme ultraviolet lithography never becomes viable. There are other options, too, such as multi-beam, which could be an alternative to multipatterning using 193nm immersion lithography.

But that’s only one part of the options menu. GlobalFoundries just had a big breakthrough in 3D stacking, rolling out a middle-via approach to TSVs that appears to make it commercially viable. Through-silicon vias have been problematic from a manufacturing standpoint because it’s like putting a giant pipe into the substrate. Having a process that is repeatable goes a long way toward offering performance improvements in designs, because the distance between two chips is often less than across a single die, and it requires less power because the pipe is larger and the distance is shorter. Moreover, there are fewer RC issues that come with thinner wires, less electromigration to deal with, and less routing congesting because memory can be approached from another dimension.

A third option is fully depleted SOI at 28nm, which avoids the need for designing finFETs. While finFETs offer major improvements in controlling leakage, similar gains can be made with FD-SOI. STMicroelectronics has made the most of that node, and many companies are expected to follow suit. By adding body biasing, ST has demonstrated similar gains to designing with finFETs.

IBM is working on all of the above. The company likely will offer finFETs on FD-SOI, possibly developed with directed self-assembly, and ultimately in stacked configurations. Others will mix and match options, depending upon the application, cost considerations, and whether it’s a platform for derivatives.

But this raises some interesting questions on the tooling and equipment side. If all of these options are available, and the complexity of each of them is rising—and subsequently the cost—then what will customers use in volume to warrant the huge investment in tools? If they opt out at 28nm using FD-SOI, then older process technology and tools work just fine. If they move to finFETs, they need more advanced EDA tools and the foundries have to invest in new equipment. And if they use stacked configurations, that poses a new set of challenges that require more advanced tools, more complicated testing and new packaging equipment.

While options are great for designers, they come with a huge price tag and many more risks for the companies that make those designs possible. End markets are fragmenting, but so are the design choices that need to be made to serve those markets.

—Ed Sperling

By Ed Sperling
Nature abhors a vacuum. Customers abhor a monopoly. It appears both problems are now being solved in the EDA world—assuming approval by regulatory agencies, of course.

There have been two concerns facing chipmakers in regards to third-party IP. One is political. Most large companies spent millions of dollars and thousands of frustrating man-hours developing their own internal IP. It’s hard to justify throwing that away in favor of commercially developed IP, and for several process nodes engineering teams have managed to tweak the heck out of it and make it work, even if the result isn’t optimal.

This approach is like patching a pair of jeans over and over again. Pretty soon they look more like patches than jeans. Now even the patches are wearing thin. For most ICs, the internally developed IP is inferior to what’s on the market, meaning the only differentiation is negative.

That’s one of the reasons that commercial IP sales are on the rise. They’re now approaching 50% of all standard IP in an SoC for some companies, and the projection is that number could rise as high as 80%. Commercial IP saves time. Most of it is extremely well tested and characterized across a large base of diverse customers, and much of it is even proven in silicon. Over the next few years, it’s likely there will be a bigger push into subsystems, as well, and while the concept isn’t new the reality is that adoption has been very limited.

Commercial IP was created to fill this vacuum, speed up time to market and focus precious engineering resources where chips really can be differentiated—software, analog/mixed signal and integration. While there has been plenty of competition in the IP processor world—total sales are now above 10 billion units per year, according to Semico Research—there has been far less traffic in the standard IP market. That’s about to change.

The reason is competition. No one likes one company to have the lion’s share of anything. In fact, it can stall a market faster than anything else. New tools are great, but it’s really tough to find any chipmaker that uses a single vendor’s integrated flow from start to finish—particularly a company with enough resources to really pick and choose what they want. Even IDMs that traditionally developed their own EDA tools have a mix of in-house and commercial tools.

In the standard IP market, Synopsys has done well so far without much direct competition from other EDA companies. As competition increases—Cadence has made its intentions rather obvious over the past couple months—the amount of commercial IP used in designs should increase dramatically. Even Mentor Graphics, which has kept a hand in the software and memory IP markets, is likely to benefit greatly from this competition, and so are companies that offer IP around the edges such as the developers of network-on-chip IP.

Customers certainly like being able to play off one company against another on price, of course, but far more important is having a reference point for IP quality from companies they can trust. One company can’t provide that, no matter how good the data. Chipmakers already are comfortable with the big EDA companies, because they rely each day on EDA tools to develop incredibly complex chips at advanced process nodes. As those EDA companies ramp up their IP capabilities, the likelihood that they also will now feel more comfortable with standard IP, and offer suggestions about how to tweak it to make it even better, is extremely high.

So let the IP wars begin. It’s the best way to grow this side of the industry, improve quality, and reduce the cost and time it takes to bring complex SoCs to market.

—Ed Sperling

Functional verification has been a consideration throughout the design flow for the past several process nodes. Low power verification has been more of an afterthought.

That’s beginning to change, though, as the challenge of integrating IP blocks and the physical effects of shrinking wires and RC delays in interconnects begin affecting power and performance in designs. What’s becoming clear increasingly clear is that understanding the impact of power—really understanding it and how to avoid problems—can directly affect performance and battery life of an entire device.

This kind of verification will always be a mind-bending challenge. Just look at user models for the ubiquitous smart phone. A person who plays graphic-intensive action games may get five hours of battery life while another user gets three days between charges because they only use it for phone calls and occasional e-mail and Internet access. And the person who works in a good reception area will get significantly better battery life than a person who doesn’t.

But those are architectural issues, and they’re relatively well understood even though addressing them isn’t so simple. The new challenge is making sure all of this is stuff is possible at the implementation level, where power has been sneaking up on design engineers one node at a time. Bunching wires around memories, packing more functionality that adds contention for buses, memories and I/O, and running things at full power for varying amounts of time can have a big impact on everything from how things are laid out to the software used to manage various blocks, subsystems, or even code deeply embedded inside of IP.

What’s changed is that this isn’t the kind of stuff that typically shows up until the implementation and integration phase of the design. While in the past it could be ignored, handed over the wall to the verification and software teams to fix, and handed off to the foundries to fix on the process side, that’s no longer possible. For one thing, foundries now charge per wafer, not per good die. For another, the functional and physical verification teams are so swamped they’re now starting to throw design problems back to design teams to fix. And software, no matter how much it has served as a Band-Aid in the past, is generally the least efficient means of solving a power issue.

As the mainstream process node slips to 40nm, these changes are really beginning to hit home at every step of the design flow. At 28nm, they have become a core consideration for everyone. And at 20nm, particularly with 14nm finFETs thrown in, they can make the difference between whether a design is successful—or whether it works at all.

—Ed Sperling

The next version of the Unified Power Format has been approved, bridging the major differences between UPF/IEEE 1801 and the Common Power Format.

For anyone who works in low-power verification, this is very good news. The new standard is the result of an unprecedented collaboration by chipmakers and EDA companies, and the people who devised a solution to this problem deserve a big pat on the back. They are the unsung heroes of the electronics world, and they have accomplished a complex accord that should make our representatives in government green with envy.

But this also begs the question, “Why were there two standards in the first place?” The blame falls on competitors jumping into the standards battle prematurely, based on the assumption that they could force customers to choose sides with their individual power formats. While it may have seemed black and white enough on paper, it never could have worked outside of a vacuum with a precise set of business conditions, namely winner take all. The reality is that large chipmakers don’t standardize on any single vendor’s tools. They don’t like being locked in, which is why there are still three big EDA vendors and lots of smaller players around the fringes.

While there were crude bridges constructed between these formats—which are the basis of most power verification efforts in complex SoCs—they were hardly perfect. And they were never complete—like bridges that crossed most of the way but never quite reached the other side. New versions of these standards were rolled out to minimize the differences, but that sometimes made the problem even worse. Instead of two standards, engineering teams were forced to contend with multiple versions of each standard and then find a way to tie them all together.

One piece of IP may have been verified with one standard, while another piece of IP was verified with another. And that was true for commercial IP as well as internally developed IP, a problem only made worse by consolidation in the IP business over the past few years.

Unfortunately, that’s still the reality in the semiconductor industry. But when the next version of UPF finally rolls out later this year—version 2.1—chances are good that we finally can put this behind us. And hopefully the EDA industry has learned a lesson about jumping on standards too early and causing their customers grief. Tools are supposed to make the job easier, but in this case tools are being created just to fix other tools. Why does that sound so wrong?

—Ed Sperling

The rule of thumb for semiconductor manufacturing is that big breakthroughs tend to last a decade, or about five process nodes. While the transistor already has spanned more than five decades and the IC more than four decades, the technology used to create them typically only lasts about one.

193nm lithography has been around more than a decade. Bets were being made publicly back at 45nm—one node after EUV originally was supposed to become commercially viable—that even immersion wouldn’t last beyond 22nm. Billions of dollars later, with more billions being sunk into getting the EUV power source up to speed, it still isn’t ready. It may never be, which is why we’re now facing double patterning issues at 20nm, and potentially triple and quadruple patterning at 14nm.

While technically this multi-patterning approach will work, it’s not very efficient to have to pattern masks three and four times. It’s not even cost-effective, and it may have an adverse impact on both performance and power. Masks essentially create seams when they’re overlaid on top of one another, and the best way to account for those seams is either through very restrictive design rules—something that makes design teams wonder why you’re moving to the next process node in the first place—or margin. At 28nm, margin was shown to affect performance and power budgets. At each new node, that effect is magnified.

One alternative to emerge is fully depleted SOI (FD-SOI), which at 28nm has provided many of the same benefits of finFETs in controlling leakage and boosting performance. ST Microelectronics is the poster child for this technology—a variant known as ultra-thin body and box—which it rolled out last year using body biasing to dynamically swap off performance and power. At 28nm, this can still be done with immersion. At the next process node, if EUV isn’t ready, ST will require double patterning, as well.

A second alternative is to improve the technology at 28nm and not move to the next node. Foundries are considering adding finFETs at 28nm to control leakage, possibly in conjunction with FD-SOI, which will provide many of the power/performance improvements of moving to the next nodes without the double patterning problem. More fins can be added to the finFET transistors to extend this approach, as well.

A third approach is stacking the die, which is particularly favored by analog IP vendors and makers of high-performance computer chips. On the IP side, it lengthens their return on investment. On the computer side, it improves performance by widening signal channels and shortening wire lengths. Many are convinced this approach will become mainstream at some point, either with 2.5D packaging or full 3D-IC approaches.

A fourth approach is to change the manufacturing process altogether. This has always been the choice of last resort because it threatens business models across the supply chain—a well-oiled machine that has overseen a steady drop in cost per transistors since the introduction of Moore’s Law. Directed self-assembly can be done using relatively inexpensive equipment. Carbon nanotubes can be grown for CNT finFETs and wrapped with a conformal gate. So far, no one knows at what speed, what cost, and with what consistency. But it’s clear they are seriously looking at alternatives right now.

No matter which path is taken—or paths—it’s clear that change is afoot. EUV’s future already is limited. The clock has been ticking since 65nm. There’s no such thing as EUV immersion. And there are enough options at various stages of development that something will likely pan out.

While all of this appears to be one step removed from the SoC design world, it still will have a significant impact on future designs. All of these efforts have a big impact on controlling leakage and improving performance, which translates into longer battery life and higher clock frequencies. These changes also could eliminate some of the physical effects headaches designers now contend with, such as electromigration and electromagnetic interference. Design and manufacturing have always been two very separate worlds with different concerns and languages, but increasingly they are becoming bit-mapped representations of each other—even if it is hard to discern that through the multiple mask layers.

—Ed Sperling

As the amount of commercially available IP in a design increases, so does the level of confusion. Unlike those giant yellow stickers you get with a major appliance that tell you how much energy you’re likely to use over the course of a year and the projected cost range, there’s no such information available for semiconductor IP.

In fact, there’s even resistance to provide that kind of information. The argument is that no two designs are alike and therefore it’s impossible to provide that level of detail. There is some merit to that argument. Still, this approach has to change for the commercial IP model to grow—and for rival IP makers to know what the target cost, power and performance metrics are that they have to beat. That’s what makes an industry competitive, but it’s also what makes companies buying that IP more inclined to put their trust behind it. And in this case, trust can be measured in tens of millions of dollars for a single design. That’s a big purchase, even by mega-company standards.

So what’s needed to make this work? In addition to data about sensitivity to noise and heat, specs are needed about how IP works at different process nodes where shrinking wires can quickly result in excessive heat and cause electromigration. How much energy does an IP block use at full power—which is a common strategy for saving power because of quick on and off—versus running at lower power. And if it isn’t operating at full power, what’s the effect on performance and the overall power budget, and what kinds of physical effects are there that could affect other components or overall performance? If it’s digital, how much noise does it generate? If it’s analog, how sensitive is it to other noise? And what’s the average speed and energy draw—similar to ratings for cars about mileage—under well-defined use cases?

The fact that businesses have capitalized on their very specific knowledge of IP and how it interacts with other IP and standard components is a model of enterprise, and it has been a necessary stopgap measure for a nascent industry. However, it doesn’t help the IP industry grow—or grow up. And with estimated annual revenues of $4 billion, and 2% to 3% compound annual growth, it’s time the IP industry began to behave like the thriving industry that it has become.

IP will always be a black box in some respects, and with the addition of subsystems those black boxes will grow even larger, be optimized for specific configurations, and offer significant improvements in performance, efficiency, integration and reliability. There’s a lot of work that goes into developing IP blocks, and even more for subsystems, and for good business reasons the exact formula needs to remain with the company that developed it. But as with Coca Cola, you don’t need to give away the recipe to remain competitive. Nevertheless, you should be able to tell how much sugar and caffeine is in it, and how many calories you’re consuming if you drink a small one versus a supersized drink. IP that goes into an SoC is no different.

The rule of thumb in the IP business is, let the buyer beware. The problem is that the buyer can only really beware if they know what they’re buying. At this point, it’s still a mystery, and that doesn’t help anyone in the long run.

—Ed Sperling