Moore’s Law Revisited
Moore’s Law, for all its re-interpretation, remains an iconic economic statement about doubling transistors over a fixed period of time—despite the fact that the time frame has changed at least twice since Gordon Moore first postulated his formula for shrinking features. Still, you don’t shrink feature sizes unless there is some economic benefit, and increasingly you don’t get an economic benefit unless power and performance are part of the equation.
It’s rather telling that Moore never mentioned power and performance, but increasingly they are becoming the primary reasons for continuing on this quest to move to the next process node. The reality is that it’s possible to shrink feature sizes to the point where we have to shift from nanometers to Angstroms, but the cost per transistor is beginning to rise from a manufacturing standpoint. Not only is classical scaling dead. Economic scaling is dying, too.
What the crossover point will be is unknown. There are still improvements that can be made in manufacturing, process and design. The addition of extreme ultraviolet lithography (EUV) will certainly help, providing it ever reaches commercially viable speeds. So will new manufacturing techniques such as directed self-assembly, better software, more standards and more re-use of IP.
But a new piece of this equation—or maybe a new equation entirely—will be less about the number of transistors and line widths between transistors and more about the markets they’re intended for and what they can offer that’s different. End markets are fragmenting at a rapid pace, and the real value in design will be to provide the right performance, the right amount of energy efficiency, and the right software and hardware to address those markets specifically. The goal is to provide exactly the right resources to the right market at the right time.
The key in this case is less about the numbers of transistors than what the transistors actually do. In a data center, for example, the focus will continue to be on power and performance and less on cost. If you can provide more performance for less power then it doesn’t matter if a chip costs an extra $100 because the savings can be in the millions of dollars. On the other hand, if it’s a smart phone for a developing market, power and total device cost will be more important than performance. And if it’s for a laptop computer, it could be any mix of these three elements depending upon who’s buying the machine.
That means the most compelling reason to move to 14nm, or to stay at 28nm using fully depleted silicon on insulator, may be about power and/or performance. And the reason to go to stacked die configurations may be less about cost initially, but more about cost as the packaging approach becomes more mainstream and more IP can be re-used. But the real measure of Moore’s Law, cost per transistor, may no longer be relevant to anyone except a handful of companies such as Intel, GPU and memory makers—and even they’re starting to rethink the equation.
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